LOGICALLY DETERMINED DESIGN -- CONTENTS -- Preface -- Acknowledgments -- 1. Trusting Logic -- 1.1 Mathematicianless Enlivenment of Logic Expression -- 1.2 Emulating the Mathematician -- 1.3 Supplementing the Expressivity of Boolean Logic -- 1.3.1 The Expressional Insufficiency of Boolean Logic -- 1.3.2 Supplementing the Logical Expression -- 1.3.3 Coordinating Combinational Expressions -- 1.3.4 The Complexity Burden of the Time Interval -- 1.3.5 Forms of Supplementation Other Than the Time Interval -- 1.3.6 The Complexity Burden of Asynchronous Design -- 1.3.7 The Cost of Supplementation -- 1.4 Defining a Sufficiently Expressive Logic -- 1.4.1 Logically Expressing Data Presentation Boundaries -- 1.4.2 Logically Recognizing Data Presentation Boundaries -- 1.4.3 Logically Coordinating the Flow of Data -- 1.4.4 Mathematicianless Completeness of Expression -- 1.5 The Logically Determined System -- 1.6 Trusting the Logic: A Methodology of Logical Confidence -- 1.7 Summary -- 1.8 Exercises -- 2. A Sufficiently Expressive Logic -- 2.1 Searching for a New Logic -- 2.1.1 Expressing Discrete Data Presentation Boundaries -- 2.1.2 Logically Recognizing Discrete Data Presentation Boundaries -- 2.1.3 The Universality of the NULL Function -- 2.1.4 Bounding the Behavior of a Combinational Expression -- 2.1.5 Relationship of 4NCL to Boolean Logic -- 2.2 Deriving a 3 Value Logic -- 2.2.1 Expressing 3NCL State-holding Behavior -- 2.2.2 3NCL Summary -- 2.3 Deriving a 2 Value Logic -- 2.3.1 The Data Differentiation Convention -- 2.3.2 2NCL as a Threshold Logic -- 2.3.3 2NCL in Relation to Boolean Logic -- 2.3.4 Subvariable Expressivity -- 2.3.5 Completeness at the Variable Level -- 2.3.6 The 2NCL Orphan Path -- 2.3.7 2NCL Summary -- 2.4 Compromising Logical Completeness -- 2.4.1 Moving Logically Determined Completeness Boundaries Farther Apart.

2.4.2 No Logically Determined Boundaries in Data Path -- 2.4.3 No Logically Determined Boundaries at All -- 2.5 Summary -- 3. The Structure of Logically Determined Systems -- 3.1 The Cycle -- 3.1.1 The Ring Oscillator -- 3.1.2 Oscillator Composition with Shared Completeness Path -- 3.1.3 Cycles and 2NCL Data Paths -- 3.1.4 Data Path Abstraction -- 3.1.5 Composition in Terms of Cycles -- 3.1.6 Composition in Terms of Registration Stages -- 3.2 Basic Pipeline Structures -- 3.2.1 Pipeline Fan-out -- 3.2.2 Pipeline Fan-in -- 3.2.3 The Pipeline Ring -- 3.2.4 Cycle Structure Example -- 3.3 Control Variables and Wavefront Steering -- 3.3.1 Steering Control Variables -- 3.3.2 Fan-out Wavefront Steering -- 3.3.3 Fan-in Wavefront Steering -- 3.3.4 Wavefront Steering Philosophy -- 3.3.5 Concurrent Pipelined Function Paths -- 3.4 The Logically Determined System -- 3.4.1 Managing Wavefront Interaction -- 3.4.2 A Simple Example System -- 3.5 Initialization -- 3.5.1 Initializing the System -- 3.5.2 Initializing Data Wavefronts -- 3.6 Testing -- 3.7 Summary -- 3.8 Exercises -- 4. 2NCL Combinational Expression -- 4.1 Function Classification -- 4.1.1 Threshold Function Classification -- 4.1.2 Boolean Function Classification -- 4.1.3 Linear Separability and Unateness -- 4.2 The Library of 2NCL Operators -- 4.3 2NCL Combinational Expression -- 4.3.1 The Two Roles of Boolean Equations -- 4.3.2 Combinational Synthesis -- 4.4 Example 1: Binary Plus Trinary to Quaternary Adder -- 4.5 Example 2: Logic Unit -- 4.6 Example 3: Minterm Construction -- 4.7 Example 4: A Binary Clipper -- 4.7.1 The Clipper Control Function -- 4.7.2 The Danger of Minimizing the Boolean Output Equations -- 4.7.3 The Clipper Data Function -- 4.8 Example 5: A Code Detector -- 4.9 Completeness Sufficiency -- 4.10 Greater Combinational Composition -- 4.10.1 Composition of Combinational Expressions.

4.10.2 The 2NCL Ripple Carry Adder -- 4.11 Directly Mapping Boolean Combinational Expressions -- 4.11.1 Mapping 2 Variable Boolean Functions -- 4.11.2 The Boolean NPN Classes and 2NCL Expressions -- 4.11.3 Mapping NPN Classes for Three-variable Boolean Functions -- 4.12 Summary -- 4.13 Exercises -- 5. Cycle Granularity -- 5.1 Partitioning Combinational Expressions -- 5.1.1 Pipeline Partitioning the Combinational Expression -- 5.1.2 Variable Partitioning the Combinational Expression -- 5.2 Partitioning the Data Path -- 5.3 Two-dimensional Pipelining: Orthogonal Pipelining Across a Data Path -- 5.4 2D Wavefront Behavior -- 5.4.1 Orthogonal Pipelining Direction -- 5.4.2 Wavefront Conflicts -- 5.4.3 Managing Wavefront Flow -- 5.4.4 Wavefront Slope Buffering -- 5.4.5 Function Structuring -- 5.5 2D Pipelined Operations -- 5.5.1 2D Pipelined Data Path Operations -- 5.5.2 2D Pipelined Control Operations -- 5.6 Summary -- 5.7 Exercises -- 6. Memory Elements -- 6.1 The Ring Register -- 6.2 Complex Function Registers -- 6.2.1 A Program Counter Register -- 6.2.2 A Counter Register -- 6.3 The Consume/Produce Register Structure -- 6.3.1 The Read Cycle -- 6.3.2 The Write Cycle -- 6.4 The Register File -- 6.4.1 A Concurrent Access Register File -- 6.4.2 2D Pipelined Register File -- 6.5 Delay Pipeline Memory -- 6.6 Delay Tower -- 6.7 FIFO Tower -- 6.8 Stack Tower -- 6.9 Wrapper for Standard Memory Modules -- 6.9.1 The Write Operation -- 6.9.2 The Read Operation -- 6.9.3 The Binary Conversions -- 6.9.4 2D Pipelined Memories -- 6.10 Exercises -- 7. State Machines -- 7.1 Basic State Machine Structure -- 7.1.1 State Sequencer -- 7.1.2 Monkey Get Banana -- 7.1.3 Code Detector -- 7.1.4 Stack Controller -- 7.2 Exercises -- 8. Busses and Networks -- 8.1 The Bus -- 8.1.1 The Serial Bus Structure -- 8.1.2 The Crossbar -- 8.2 A Fan-out Steering Tree.

8.3 Fan-in Steering Trees Do Not Work -- 8.4 Arbitrated Steering Structures -- 8.4.1 The MUTEX -- 8.4.2 The Arbiter -- 8.4.3 An Arbitrated 2 to 1 Fan-in -- 8.4.4 Arbiter Simulation -- 8.4.5 Arbiter Timing Issues -- 8.5 Concurrent Crossbar Network -- 8.5.1 The Arbitrated Crossbar Cell -- 8.5.2 2D Pipelining Arbitrated Control Variables -- 8.6 Exercises -- 9. Multi-value Numeric Design -- 9.1 Numeric Representation -- 9.1.1 Resource Cost of Transmission -- 9.1.2 Energy Cost of Transmission -- 9.1.3 Combined Transmission Costs -- 9.1.4 Resource Cost of Combination -- 9.1.5 Energy Cost of Combination -- 9.1.6 Combined Cost for Numeric Combination -- 9.1.7 Summary of Multi-path Numeric Representation -- 9.2 A Quaternary ALU -- 9.3 A Binary ALU -- 9.4 Comparison -- 9.5 Summary -- 9.6 Exercises -- 10. The Shadow Model of Pipeline Behavior -- 10.1 Pipeline Structure -- 10.1.1 The Cycle Path and the Cycle Period -- 10.1.2 The Wavefront Path: Forward Latency -- 10.1.3 The Bubble Path: Reverse Latency -- 10.2 The Pipeline Simulation Model -- 10.3 Delays Affecting Throughput -- 10.4 The Shadow Model -- 10.4.1 Shadowed Equal Delays -- 10.4.2 Unshadowed Delays -- 10.4.3 Shadow Intersection -- 10.4.4 A More Complex Example -- 10.5 The Value of the Shadow Model -- 10.5.1 The Consistently Slow Cycle -- 10.5.2 The Occasional Slow Cycle -- 10.6 Exercises -- 11. Pipeline Buffering -- 11.1 Enhancing Throughput -- 11.1.1 Buffer Structuring for Throughput -- 11.1.2 Correlated Variable Cycle Behavior -- 11.1.3 Summary of Throughput Buffering -- 11.2 Buffering for Constant Rate Throughput -- 11.2.1 The Buffering Behavior -- 11.2.2 The Competition -- 11.2.3 The Battle of Intersecting Shadows -- 11.2.4 The Standoff -- 11.2.5 Summary of Buffering for Constant Rate Throughput -- 11.3 Summary of Buffering -- 11.4 Exercises -- 12. Ring Behavior -- 12.1 The Pipeline Ring.

12.2 Wavefront-limited Ring Behavior -- 12.2.1 Bubble-limited Ring Behavior -- 12.2.2 Delay-limited Ring Behavior -- 12.2.3 Perfectly Balanced Ring Behavior -- 12.3 The Cycle-to-Wavefront Ratio -- 12.4 Ring Signal Behavior -- 13. Interacting Pipeline Structures -- 13.1 Preliminaries -- 13.2 Example 1: The Basics of a Two-pipeline Structure -- 13.2.1 Basics of Flow -- 13.2.2 Increasing the Throughput -- 13.2.3 Summary of Example 1 -- 13.3 Example 2: A Wavefront Delay Structure -- 13.3.1 Analysis of Delay Structure -- 13.3.2 Summary of Example 2 -- 13.4 Example 3: Reducing the Period of the Slowest Cycle -- 13.4.1 Finer Grained Pipelining -- 13.4.2 Optimizing the Logic -- 13.5 Exercises -- 14. Complex Pipeline Structures -- 14.1 Linear Feedback Shift Register Example -- 14.2 Grafting Pipelines -- 14.2.1 Step 1 -- 14.2.2 Step 2 -- 14.2.3 Step 3 -- 14.2.4 Step 4 -- 14.2.5 Step 5 -- 14.2.6 Step 6 -- 14.2.7 Step 7 -- 14.2.8 Step 8 -- 14.2.9 Step 9 -- 14.2.10 Summary of Results -- 14.3 The LFSR with a Slow Cycle -- 14.4 Summary -- 14.5 Exercises -- Appendix A: Logically Determined Wavefront Flow -- A.1 Synchronization -- A.2 Wavefronts and Bubbles -- A.3 Wavefront Propagation -- A.4 Extended Simulation of Wavefront Flow -- A.5 Wavefront and Bubble Behavior in a System -- Appendix B: Playing with 2NCL -- B.1 The SR Flip-flop Implementations -- B.2 Initialization -- B.3 Auto-produce and Auto-consume -- Appendix C: Pipeline Simulation -- References -- Index.