Front Cover -- Customizable Embedded Processors -- Copyright Page -- Contents -- In Praise of Customizable Embedded Processors -- List of Contributors -- About the Editors -- Part I: Opportunities and Challenges -- Chapter 1. From Prêt-à-Porter to Tailor-Made -- 1.1 The Call for Flexibility -- 1.2 Cool Chips for Shallow Pockets -- 1.3 A Million Processors for the Price of One? -- 1.4 Processors Coming of Age -- 1.5 This Book -- 1.6 Travel Broadens the Mind -- Chapter 2. Opportunities for Application-Specific Processors: The Case of Wireless Communications -- 2.1 Future Mobile Communication Systems -- 2.2 Heterogeneous MPSoC for Digital Receivers -- 2.3 ASIP Design -- Chapter 3. Customizing Processors: Lofty Ambitions, Stark Realities -- 3.1 The "CFP" project at HP Labs -- 3.2 Searching for the Best Architecture Is Not a Machine-Only Endeavor -- 3.3 Designing a CPU Core Still Takes a Very Long Time -- 3.4 Don't Underestimate Competitive Technologies -- 3.5 Software Developers Don't Always Help You -- 3.6 The Embedded World Is Not Immune to Legacy Problems -- 3.7 Customization Can Be Trouble -- 3.8 Conclusions -- Part II: Aspects of Processor Customization -- Chapter 4. Architecture Description Languages -- 4.1 ADLs and other languages -- 4.2 Survey of Contemporary ADLs -- 4.3 Conclusions -- Chapter 5. C Compiler Retargeting -- 5.1 Compiler Construction Background -- 5.2 Approaches to Retargetable Compilation -- 5.3 Processor Architecture Exploration -- 5.4 C Compiler Retargeting in the LISATek Platform -- 5.5 Summary and Outlook -- Chapter 6. Automated Processor Configuration and Instruction Extension -- 6.1 Automation Is Essential for ASIP Proliferation -- 6.2 The Tensilica Xtensa LX Configurable Processor -- 6.3 Generating ASIPs Using Xtensa -- 6.4 Automatic Generation of ASIP Specifications.

6.5 Coding an Application for Automatic ASIP Generation -- 6.6 XPRES Benchmarking Results -- 6.7 Techniques for ASIP Generation -- 6.8 Exploring the Design Space -- 6.9 Evaluating Xpres Estimation Methods -- 6.10 Conclusions and Future of the Technology -- Chapter 7. Automatic Instruction-Set Extensions -- 7.1 Beyond Traditional Compilers -- 7.2 Building Block for Instruction Set Extension -- 7.3 Heuristics -- 7.4 State-Holding Instruction-Set Extensions -- 7.5 Exploiting Pipelining to Relax I/O Constraints -- 7.6 Conclusions and Further Challenges -- Chapter 8. Challenges to Automatic Customization -- 8.1 The ARCompactTM Instruction Set Architecture -- 8.2 Microarchitecture Challenges -- 8.3 Case Study-Entropy Decoding -- 8.4 Limitations of Automated Extension -- 8.5 The Benefits of Architecture Extension -- 8.6 Conclusions -- Chapter 9. Coprocessor Generation from Executable Code -- 9.1 Introduction -- 9.2 User Level Flow -- 9.3 Integration with Embedded Software -- 9.4 Coprocessor Architecture -- 9.5 ILP Extraction Challenges -- 9.6 Internal Tool Flow -- 9.7 Code Mapping Approach -- 9.8 Synthesizing Coprocessor Architectures -- 9.9 A Real-World Example -- 9.10 Summary -- Chapter 10. Datapath Synthesis -- 10.1 Introduction -- 10.2 Custom Instruction Selection -- 10.3 Theoretical Preliminaries -- 10.4 Minimum Area-Cost Acyclic Common Supergraph Heuristic -- 10.5 Multiplexer Insertion -- 10.6 Datapath Synthesis -- 10.7 Experimental Results -- 10.8 Conclusion -- Chapter 11. Instruction Matching and Modeling -- 11.1 Matching Instructions -- 11.2 Modeling -- 11.3 Conclusions -- Chapter 12. Processor Verification -- 12.1 Motivation -- 12.2 Overview of Verification Approaches -- 12.3 Formal Verification of a RISC CPU -- 12.4 Verification Challenges in Customizable and Configurable Embedded Processors -- 12.5 Verification of Processor Peripherals.

12.6 Conclusions -- Chapter 13. Sub-RISC Processors -- 13.1 Concurrent Architectures, Concurrent Applications -- 13.2 Motivating Sub-RISC PEs -- 13.3 Designing TIPI Processing Elements -- 13.4 Deploying Applications with Cairn -- 13.5 IPv4 Forwarding Design Example -- 13.6 Performance Results -- 13.7 Conclusion -- Part III: Case Studies -- Chapter 14. Application Specific Instruction Set Processor for UMTS-FDD Cell Search -- 14.1 ASIP on Wireless Modem Design -- 14.2 Functionality of Cell Search ASIP -- 14.3 Cell Search ASIP Design and Verification -- 14.4 Results -- 14.5 Summary and Conclusions -- Chapter 15. Hardware/Software Tradeoffs for Advanced 3G Channel Decoding -- 15.1 Channel Decoding for 3G Systems and Beyond -- 15.2 Design Space -- 15.3 Programmable Solutions -- 15.4 Multiprocessor Architectures -- 15.5 Conclusion -- Chapter 16. Application Code Profiling and ISA Synthesis on MIPS32 -- 16.1 Profiling of Application Source Code -- 16.2 Semi-Automatic ISA Extension Synthesis -- 16.3 Summary and Outlook -- Chapter 17. Designing Soft Processors for FPGAs -- 17.1 Overview -- 17.2 MicroBlaze Soft Processor Architecture -- 17.3 Discussion of Architectural Design Tradeoffs in MicroBlaze -- 17.4 Conclusions -- Chapter References -- Bibliography -- Index.