Contents -- Foreword -- Preface -- List of Symbols -- Acronyms -- 1 Overview -- 1.1 Circuit Design with MOSFETs -- 1.2 MOSFET Modeling -- 1.3 Model Parameter Determination -- 1.4 Interconnect Modeling -- 1.5 Subjects Covered -- References -- 2 Review of Basic Semiconductor and pn Junction Theory -- 2.1 Energy Band Model -- 2.2 Intrinsic Semiconductor -- 2.2.1 Fermi level -- 2.3 Extrinsic or Doped Semiconductor -- 2.3.1 Generation-Recombination -- 2.3.2 Quasi-Fermi Level -- 2.4 Electrical Conduction -- 2.4.1 Carrier Mobility -- 2.4.2 Resistivity and Sheet Resistance -- 2.4.3 Transport Equations -- 2.4.4 Continuity Equation -- 2.4.5 Poisson's Equation -- 2.5 pn Junction at Equilibrium -- 2.5.1 Built-in Potential -- 2.5.2 Depletion Width -- 2.6 Diode Current-Voltage Characteristics -- 2.6.1 Limitation of the Diode Current Model -- 2.6.2 Bulk Resistance -- 2.6.3 Junction Breakdown Voltage -- 2.7 Diode Dynamic Behavior -- 2.7.1 Junction Capacitance -- 2.7.2 Diffusion Capacitance -- 2.7.3 Small Signal Conductance -- 2.8 Real pn Junction -- 2.9 Diode Circuit Model -- 2.10 Temperature Dependent Diode Model Parameters -- 2.10.1 Temperature Dependence of I , -- 2.10.2 Temperature Dependence of 4bi -- 2.10.3 Temperature Dependence of Cjo -- References -- 3 MOS Transistor Structure and Operation -- 3.1 MOSFET Structure -- 3.2 MOSFET Characteristics -- 3.2.1 Punchthrough -- 3.2.2 MOSFET Capacitances -- 3.2.3 Small-Signal Behavior -- 3.2.4 Device Speed -- 3.3 MOSFET Scaling -- 3.4 Hot-Carrier Effects -- 3.5 VLSI Device Structures -- 3.5.1 Gate Material -- 3.5.2 Nonuniform Channel Doping -- 3.5.3 Source-Drain Structures -- 3.5.4 Device Isolation -- 3.5.5 CMOS Process -- 3.6 MOSFET Parasitic Elements -- 3.6.1 Source-Drain Resistance -- 3.6.2 Source/Drain Junction Capacitance -- 3.6.3 Gate Overlap Capacitances -- 3.7 MOSFET Length and Width Definitions.

3.7.1 Effective or Electrical Channel Length -- 3.7.2 Effective or Electrical Channel Width -- 3.8 MOSFET Circuit Models -- References -- 4 MOS Capacitor -- 4.1 MOS Capacitor with No Applied Voltage -- 4.1.1 Work Function -- 4.1.2 Oxide Charges -- 4.1.3 Flat Band Voltage -- 4.2 MOS Capacitor at Non-Zero Bias -- 4.2.1 Accumulation -- 4.2.2 Depletion -- 4.2.3 Inversion -- 4.3 Capacitance of MOS Structures -- 4.3.1 Low Frequency C-V Plot -- 4.3.2 High Frequency C-V Plot -- 4.3.3 Deep Depletion C-V Plot -- 4.4 Deviation from Ideal C-V Curves -- 4.5 Anomalous C-V Curve (Polysilicon Depletion Effect) -- 4.6 MOS Capacitor Applications -- 4.7 Nonuniformly Doped Substrate and Flat Band Voltage -- 4.7.1 Temperature Dependence of Vfb -- References -- 5 Threshold Voltage -- 5.1 MOSFET with Uniformly Doped Substrate -- 5.2 Nonuniformly Doped MOSFET -- 5.2.1 Enhancement Type Device -- 5.2.2 Depletion Type Device -- 5.3 Threshold Voltage Variations with Device Length and Width -- 5.3.1 Short-Channel Effect -- 5.3.2 Narrow-Width Effect -- 5.3.3 Drain Induced Barrier Lowering (DIBL) Effect -- 5.3.4 Small-Geometry Effect -- 5.4 Temperature Dependence of the Threshold voltage -- References -- 6 MOSFET DC Model -- 6.1 Drain Current Calculations -- 6.2 Pao-Sah Model -- 6.3 Charge-Sheet Model -- 6.4 Piece-Wise Drain Current Model for Enhancement Devices -- 6.4.1 First Order Model -- 6.4.2 Bulk-Charge Model -- 6.4.3 Square-Root Approximation -- 6.4.4 Drain Current Equation with Square-Root Approximation -- 6.4.5 Subthreshold Region Model -- 6.4.6 Limitations of the Model -- 6.5 Drain Current Model for Depletion Devices -- 6.6 Effective Mobility -- 6.6.1 Mobility Degradation Due to the Gate Voltage -- 6.6.2 Mobility Degradation Due to the Drain Voltage -- 6.7 Short-Geometry Models -- 6.7.1 Linear Region Model -- 6.7.2 Saturation Voltage.

6.7.3 Saturation Region-Channel Length Modulation -- 6.7.4 Subthreshold Model -- 6.7.5 Continuous Model -- 6.8 Impact of Source-Drain Resistance on Drain Current -- 6.9 Temperature Dependence of the Drain Current -- 6.9.1 Temperature Dependence of Mobility -- References -- 7 Dynamic Model -- 7.1 Intrinsic Charges and Capacitances -- 7.1.1 Meyer Model -- 7.1.2 Drawbacks of the Meyer Model -- 7.2 Charge-Based Capacitance Model -- 7.3 Long-Channel Charge Model -- 7.3.1 Capacitances -- 7.4 Short-Channel Charge Model -- 7.4.1 Capacitances -- 7.5 Limitations of the Quasi-Static Model -- 7.6 Small-Signal Model Parameters -- References -- 8 Modeling Hot-Carrier Effects -- 8.1 Substrate Current Model -- 8.2 Gate Current Model -- 8.3 Correlation of Gate and Substrate Current -- 8.4 Mechanism of MOSFET Degradation -- 8.5 Measure of Degradation-Device Lifetime -- 8.6 Impact of Degradation on Circuit Performance -- 8.7 Temperature Dependence of Device Degradation -- References -- 9 Data Acquisition and Model Parameter Measurements -- 9.1 Data Acquisition -- 9.1.1 Data for DC Models -- 9.1.2 Data for AC Models -- 9.1.3 MOS Capacitor C-V Measurement -- 9.2 Gate-Oxide Capacitance Measurement -- 9.2.1 Optical Method-Ellipsometry -- 9.2.2 Electrical Method -- 9.3 Measurement of Doping Profile in Silicon -- 9.3.1 Capacitance-Voltage Method -- 9.3.2 DC Method -- 9.4 Measurement of Threshold Voltage -- 9.5 Determination of Body Factor -- 9.6 Flat Band Voltage -- 9.7 Drain Induced Barrier Lowering (DIBL) Parameter -- 9.8 Determination of Subthreshold Slope -- 9.9 Carrier Inversion Layer Mobility Measurement -- 9.9.1 Split-CV Method -- 9.10 Determination of Effective Channel Length and Width -- 9.10.1 Drain Current Methods of Determination L -- 9.10.2 Capacitance Method of Determining L -- 9.10.3 Methods of Determining W -- 9.11 Determination of Drain Saturation Voltage.

9.12 Measurement of MOSFET Intrinsic Capacitances -- 9.12.1 On-Chip Methods -- 9.12.2 Off-Chip Methods -- 9.13 Measurement of Gate Overlap Capacitance -- 9.14 Measurement of MOSFET Source/Drain Diode Junction Parameters -- 9.14.1 Diode Saturation or Reverse Current I, -- 9.14.2 Junction Capacitance -- References -- 10 Model Parameter Extraction Using Optimization Method -- 10.1 Model Parameter Extraction -- 10.2 Basics Definitions in Optimization -- 10.3 Optimization Methods -- 10.3.1 Constrained Optimization -- 10.3.2 Multiple Response Optimization -- 10.4 Some Remarks on Parameter Extraction Using Optimization Technique -- 10.5 Confidence Limits on Estimated Model Parameter -- 10.5.1 Examples of Redundant Parameters -- 10.6 Parameter Extraction Using Optimizer -- 10.6.1 Drain Current Model Parameter Extraction -- 10.6.2 MOSFET AC Model Parameter Extraction -- References -- 11 SPICE Diode and MOSFET Models and Their Parameters -- 11.1 Diode Model -- 11.2 MOSFET Level 1 Model -- 11.2.1 DC Model -- 11.2.2 Capacitance Model -- 11.3 MOSFET Level 2 Model -- 11.3.1 DC Model -- 11.3.2 Capacitance Model -- 11.4 MOSFET Level 3 Model -- 11.4.1 DC Model -- 11.5 MOSFET Level 4 Model -- 11.5.1 DC Model -- 11.5.2 Capacitance Model -- 11.6 Comparison of the Four MOSFET Models -- References -- 12 Statistical Modeling and Worst-case Design Parameters -- 12.1 Methods of Generating Worst Case Parameters -- 12.2 Model Parameter Sensitivity -- 12.2.1 Principal Factor Method -- 12.3 Statistical Analysis with Parameter Correlation -- 12.3.1 Principal Component Analysis -- 12.4 Factor Analysis -- 12.4.1 Factor Rotation -- 12.4.2 Regression Models -- 12.5 Optimization Method -- References -- Appendix A. Important Properties of Silicon, Silicon Dioxide and Silicon Nitride at 300K -- Appendix B. Some Important Physical Constants at 300 K -- Appendix C. Unit Conversion Factors.

Appendix D. Magnitude Prefixes -- Appendix E. Methods of Calculating s from the Implicit Eq. (6.23) or (6.30) -- References -- Appendix F. Charge Based MOSFET Intrinsic Capacitances -- Appendix G. Linear Regression -- Reference -- Appendix H. Basic Statistical and Probability Theory -- References -- Appendix I. List of Widely Used Statistical Package Programs -- Reference -- Subject Index.