
Communicating Process Architectures 2007 : WoTUG-30.
Title:
Communicating Process Architectures 2007 : WoTUG-30.
Author:
McEwan, A.A.
ISBN:
9781607502616
Personal Author:
Physical Description:
1 online resource (528 pages)
Series:
Concurrent Systems Engineering Series
Contents:
Title page -- Preface -- Programme Committee -- Additional Reviewers -- Contents -- Fine-Grain Concurrency -- Communicating Process Architecture for Multicores -- Lazy Exploration and Checking of CSP Models with CSPsim -- The Core Language of Aldwych -- JCSProB: Implementing Integrated Formal Specifications in Concurrent Java -- Components with Symbolic Transition Systems: A Java Implementation of Rendezvous -- Concurrent/Reactive System Design with Honeysuckle -- CSP and Real-Time: Reality or Illusion? -- Testing and Sampling Parallel Systems -- Mobility in JCSP: New Mobile Channel and Mobile Process Models -- C++CSP2: A Many-to-Many Threading Model for Multicore Architectures -- Design Principles of the SystemCSP Software Framework -- PyCSP - Communicating Sequential Processes for Python -- A Process-Oriented Architecture for Complex System Modelling -- Concurrency Control and Recovery Management for Open e-Business Transactions -- trancell - An Experimental ETC to Cell BE Translator -- A Versatile Hardware-Software Platform for In-Situ Monitoring Systems -- High Cohesion and Low Coupling: The Office Mapping Factor -- A Process Oriented Approach to USB Driver Development -- A Native Transterpreter for the LEGO Mindstorms RCX -- Integrating and Extending JCSP -- Hardware/Software Synthesis and Verification Using Esterel -- Modeling and Analysis of the AMBA Bus Using CSP and B -- A Step Towards Refining and Translating B Control Annotations to Handel-C -- Towards the Formal Verification of a Java Processor in Event-B -- Advanced System Simulation, Emulation and Test (ASSET) -- Development of a Family of Multi-Core Devices Using Hierarchical Abstraction -- Domain Specific Transformations for Hardware Ray Tracing -- A Reconfigurable System-on-Chip Architecture for Pico-Satellite Missions -- Transactional CSP Processes.
Algebras of Actions in Concurrent Processes -- Using occam-pi Primitives with the Cell Broadband Engine -- Shared-Memory Multi-Processor Scheduling Algorithms for CCSP -- Compiling occam to C with Tock -- Author Index.
Abstract:
This publication deals with Computer Science and models of Concurrency. It particularly emphasises on hardware/software co-design, and the understanding of concurrency that results from these systems. A range of papers on this topic have been included, from the formal modeling of buses in co-design systems through to software simulation and development environments. The book includes a contribution by Professor Sir Tony Hoare (FRS), the founding father of the theoretical basis upon which much of the work in this series is based. He shares new thoughts on fine-grained concurrency. Another important contribution is by Professor David May (FRS) on his new architecture for massively multicore processors, its underlying programming model and applications. The editors trust you will find this publication informative and inspirational.
Local Note:
Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2017. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries.
Genre:
Electronic Access:
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