Front Cover -- System-on-Chip Test Architectures -- Copyright Page -- Table of Contents -- Preface -- In the Classroom -- Acknowledgments -- Contributors -- About the Editors -- Chapter 1 Introduction -- 1.1 Importance of System-on-Chip Testing -- 1.1.1 Yield and Reject Rate -- 1.1.2 Reliability and System Availability -- 1.2 Basics of SOC Testing -- 1.2.1 Boundary Scan (IEEE 1149.1 Standard) -- 1.2.2 Boundary Scan Extension (IEEE 1149.6 Standard) -- 1.2.3 Boundary-Scan Accessible Embedded Instruments (IEEE P1687) -- 1.2.4 Core-Based Testing (IEEE 1500 Standard) -- 1.2.5 Analog Boundary Scan (IEEE 1149.4 Standard) -- 1.3 Basics of Memory Testing -- 1.4 SOC Design Examples -- 1.4.1 BioMEMS Sensor -- 1.4.2 Network-on-Chip Processor -- 1.5 About This Book -- 1.5.1 DFT Architectures -- 1.5.2 New Fault Models and Advanced Techniques -- 1.5.3 Yield and Reliability Enhancement -- 1.5.4 Nanotechnology Testing Aspects -- 1.6 Exercises -- Acknowledgments -- References -- Chapter 2 Digital Test Architectures -- 2.1 Introduction -- 2.2 Scan Design -- 2.2.1 Scan Architectures -- 2.2.1.1 Muxed-D Scan Design -- 2.2.1.2 Clocked-Scan Design -- 2.2.1.3 LSSD Scan Design -- 2.2.1.4 Enhanced-Scan Design -- 2.2.2 Low-Power Scan Architectures -- 2.2.2.1 Reduced-Voltage Low-Power Scan Design -- 2.2.2.2 Reduced-Frequency Low-Power Scan Design -- 2.2.2.3 Multi-Phase or Multi-Duty Low-Power Scan Design -- 2.2.2.4 Bandwidth-Matching Low-Power Scan Design -- 2.2.2.5 Hybrid Low-Power Scan Design -- 2.2.3 At-Speed Scan Architectures -- 2.3 Logic Built-In Self-Test -- 2.3.1 Logic BIST Architectures -- 2.3.1.1 Self-Testing Using MISR and Parallel SRSG (STUMPS) -- 2.3.1.2 Concurrent Built-In Logic Block Observer (CBILBO) -- 2.3.2 Coverage-Driven Logic BIST Architectures -- 2.3.2.1 Weighted Pattern Generation -- 2.3.2.2 Test Point Insertion -- 2.3.2.3 Mixed-Mode BIST.

2.3.2.4 Hybrid BIST -- 2.3.3 Low-Power Logic BIST Architectures -- 2.3.3.1 Low-Transition BIST Design -- 2.3.3.2 Test-Vector-Inhibiting BIST Design -- 2.3.3.3 Modified LFSR Low-Power BIST Design -- 2.3.4 At-Speed Logic BIST Architectures -- 2.3.4.1 Single-Capture -- 2.3.4.2 Skewed-Load -- 2.3.4.3 Double-Capture -- 2.3.5 Industry Practices -- 2.4 Test Compression -- 2.4.1 Circuits for Test Stimulus Compression -- 2.4.1.1 Linear-Decompression-Based Schemes -- 2.4.1.2 Broadcast-Scan-Based Schemes -- 2.4.1.3 Comparison -- 2.4.2 Circuits for Test Response Compaction -- 2.4.2.1 Space Compaction -- 2.4.2.2 Time Compaction -- 2.4.2.3 Mixed Time and Space Compaction -- 2.4.3 Low-Power Test Compression Architectures -- 2.4.4 Industry Practices -- 2.5 Random-Access Scan Design -- 2.5.1 Random-Access Scan Architectures -- 2.5.1.1 Progressive Random-Access Scan Design -- 2.5.1.2 Shift-Addressable Random-Access Scan Design -- 2.5.2 Test Compression RAS Architectures -- 2.5.3 At-Speed RAS Architectures -- 2.6 Concluding Remarks -- 2.7 Exercises -- Acknowledgments -- References -- Chapter 3 Fault-Tolerant Design -- 3.1 Introduction -- 3.2 Fundamentals of Fault Tolerance -- 3.2.1 Reliability -- 3.2.2 Mean Time to Failure (MTTF) -- 3.2.3 Maintainability -- 3.2.4 Availability -- 3.3 Fundamentals of Coding Theory -- 3.3.1 Linear Block Codes -- 3.3.2 Unidirectional Codes -- 3.3.2.1 Two-Rail Codes -- 3.3.2.2 Berger Codes -- 3.3.2.3 Constant Weight Codes -- 3.3.3 Cyclic Codes -- 3.4 Fault Tolerance Schemes -- 3.4.1 Hardware Redundancy -- 3.4.1.1 Static Redundancy -- 3.4.1.2 Dynamic Redundancy -- 3.4.1.3 Hybrid Redundancy -- 3.4.2 Time Redundancy -- 3.4.2.1 Repeated Execution -- 3.4.2.2 Multiple Sampling of Outputs -- 3.4.2.3 Diverse Recomputation -- 3.4.3 Information Redundancy -- 3.4.3.1 Error Detection -- 3.4.3.2 Error Correction -- 3.5 Industry Practices.

3.6 Concluding Remarks -- 3.7 Exercises -- Acknowledgments -- References -- Chapter 4 System/Network-on-Chip Test Architectures -- 4.1 Introduction -- 4.2 System-on-Chip (SOC) Testing -- 4.2.1 Modular Testing of SOCs -- 4.2.2 Wrapper Design and Optimization -- 4.2.3 TAM Design and Optimization -- 4.2.4 Test Scheduling -- 4.2.5 Modular Testing of Mixed-Signal SOCs -- 4.2.6 Modular Testing of Hierarchical SOCs -- 4.2.7 Wafer-Sort Optimization for Core-Based SOCs -- 4.3 Network-on-Chip (NOC) Testing -- 4.3.1 NOC Architectures -- 4.3.2 Testing of Embedded Cores -- 4.3.2.1 Reuse of On-Chip Network for Testing -- 4.3.2.2 Test Scheduling -- 4.3.2.3 Test Access Methods and Test Interface -- 4.3.2.4 Efficient Reuse of Network -- 4.3.2.5 Power-Aware and Thermal-Aware Testing -- 4.3.3 Testing of On-Chip Networks -- 4.3.3.1 Testing of Interconnect Infrastructures -- 4.3.3.2 Testing of Routers -- 4.3.3.3 Testing of Network Interfaces and Integrated System Testing -- 4.4 Design and Test Practice: Case Studies -- 4.4.1 SOC Testing for PNX8550 System Chip -- 4.4.2 NOC Testing for a High-End TV System -- 4.5 Concluding Remarks -- 4.6 Exercises -- Acknowledgments -- References -- Chapter 5 SIP Test Architectures -- 5.1 Introduction -- 5.1.1 SIP Definition -- 5.1.2 SIP Examples -- 5.1.3 Yield and Quality Challenges -- 5.1.4 Test Strategy -- 5.2 Bare Die Test -- 5.2.1 Mechanical Probing Techniques -- 5.2.2 Electrical Probing Techniques -- 5.2.3 Reliability Screens -- 5.3 Functional System Test -- 5.3.1 Path-Based Testing -- 5.3.2 Loopback Techniques: DFT and DSP -- 5.4 Test of Embedded Components -- 5.4.1 SIP Test Access Port -- 5.4.2 Interconnections -- 5.4.3 Digital and Memory Dies -- 5.4.4 Analog and RF Components -- 5.4.4.1 Test Equipment Issues -- 5.4.4.2 Test of Analog, Mixed-Signal, and RF Dies -- 5.4.5 MEMS -- 5.5 Concluding Remarks -- 5.6 Exercises.

Acknowledgments -- References -- Chapter 6 Delay Testing -- 6.1 Introduction -- 6.2 Delay Test Application -- 6.2.1 Enhanced Scan -- 6.2.2 Muxed-D Scan -- 6.2.3 Scan Clocking -- 6.2.4 Faster-Than-At-Speed Testing -- 6.3 Delary Fault Models -- 6.3.1 Transition Fault Model -- 6.3.2 Inline-Delay Fault Model -- 6.3.3 Gate-Delay Fault Model -- 6.3.4 Path-Delay Fault Model -- 6.3.5 Defect-Based Delay Fault Models -- 6.4 Delay Test Sensitization -- 6.5 Delay Fault Simulation -- 6.5.1 Transition Fault Simulation -- 6.5.2 Gate/Line Delay Fault Simulation -- 6.5.3 Path-Delay Fault Simulation -- 6.5.4 Defect-Based Delay Fault Model Simulation -- 6.6 Delay Fault Test Generation -- 6.6.1 Transition/Inline Fault ATPG -- 6.6.2 Gate-Delay Fault ATPG -- 6.6.3 Path-Delay Fault ATPG -- 6.6.4 K Longest Paths per Gate (KLPG) ATPG -- 6.7 Pseudo-Functional Testing to Avoid Over-Testing -- 6.7.1 Computing Constraints -- 6.7.1.1 Pair-Wise Constraints -- 6.7.1.2 Multiliteral Constraints -- 6.7.2 Constrained ATPG -- 6.8 Concluding Remarks -- 6.9 Exercises -- Acknowledgments -- References -- Chapter 7 Low-Power Testing -- 7.1 Introduction -- 7.2 Energy and Power Modeling -- 7.2.1 Basics of Circuit Theory -- 7.2.2 Terminology -- 7.2.3 Test-Power Modeling and Evaluation -- 7.3 Test Power Issues -- 7.3.1 Thermal Effects -- 7.3.2 Noise Phenomena -- 7.3.3 Miscellaneous Issues -- 7.4 Low-Power Scan Testing -- 7.4.1 Basics of Scan Testing -- 7.4.2 ATPG and X-Filling Techniques -- 7.4.3 Low-Power Test Vector Compaction -- 7.4.4 Shift Control Techniques -- 7.4.5 Scan Cell Ordering -- 7.4.6 Scan Architecture Modification -- 7.4.7 Scan Clock Splitting -- 7.5 Low-Power Built-In Self-Test -- 7.5.1 Basics of Logic BIST -- 7.5.2 LFSR Tuning -- 7.5.3 Low-Power Test Pattern Generators -- 7.5.4 Vector Filtering BIST -- 7.5.5 Circuit Partitioning -- 7.5.6 Power-Aware Test Scheduling.

7.6 Low-Power Test Data Compression -- 7.6.1 Coding-Based Schemes -- 7.6.2 Linear-Decompression-Based Schemes -- 7.6.3 Broadcast-Scan-Based Schemes -- 7.7 Low-Power RAM Testing -- 7.8 Concluding Remarks -- 7.9 Exercises -- Acknowledgments -- References -- Chapter 8 Coping with Physical Failures, Soft Errors, and Reliability Issues -- 8.1 Introduction -- 8.2 Signal Integrity -- 8.2.1 Basic Concept of Integrity Loss -- 8.2.2 Sources of Integrity Loss -- 8.2.2.1 Interconnects -- 8.2.2.2 Power Supply Noise -- 8.2.2.3 Process Variations -- 8.2.3 Integrity Loss Sensors/Monitors -- 8.2.3.1 Current Sensor -- 8.2.3.2 Power Supply Noise Monitor -- 8.2.3.3 Noise Detector (ND) Sensor -- 8.2.3.4 Integrity Loss Sensor (ILS) -- 8.2.3.5 Jitter Monitor -- 8.2.3.6 Process Variation Sensor -- 8.2.4 Readout Architectures -- 8.2.4.1 BIST-Based Architecture -- 8.2.4.2 Scan-Based Architecture -- 8.2.4.3 PV-Test Architecture -- 8.3 Manufacturing Defects, Process Variations, and Reliability -- 8.3.1 Fault Detection -- 8.3.1.1 Structural Tests -- 8.3.1.2 Defect-Based Tests -- 8.3.1.3 Functional Tests -- 8.3.2 Reliability Stress -- 8.3.3 Redundancy and Memory Repair -- 8.3.4 Process Sensors and Adaptive Design -- 8.3.4.1 Process Variation Sensor -- 8.3.4.2 Thermal Sensor -- 8.3.4.3 Dynamic Voltage Scaling -- 8.4 Soft Errors -- 8.4.1 Sources of Soft Errors and SER Trends -- 8.4.2 Coping with Soft Errors -- 8.4.2.1 Fault Tolerance -- 8.4.2.2 Error-Resilient Microarchitectures -- 8.4.2.3 Soft Error Mitigation -- 8.5 Defect and Error Tolerance -- 8.5.1 Defect Tolerance -- 8.5.2 Error Tolerance -- 8.6 Concluding Remarks -- 8.7 Exercises -- Acknowledgments -- References -- Chapter 9 Design for Manufacturability and Yield -- 9.1 Introduction -- 9.2 Yield -- 9.3 Components of Yield -- 9.3.1 Yield Models -- 9.3.2 Yield and Repair -- 9.4 Photolithography -- 9.5 DFM and DFY.

9.5.1 Photolithography.