FPGA PROTOTYPING BY VHDL EXAMPLES: Xilinx Spartan™-3 Version -- Contents -- Preface -- Acknowledgments -- PART I BASIC DIGITAL CIRCUITS -- 1 Gate-level combinational circuit -- 1.1 Introduction -- 1.2 General description -- 1.2.1 Basic lexical rules -- 1.2.2 Library and package -- 1.2.3 Entity declaration -- 1.2.4 Data type and operators -- 1.2.5 Architecture body -- 1.2.6 Code of a 2-bit comparator -- 1.3 Structural description -- 1.4 Testbench -- 1.5 Bibliographic notes -- 1.6 Suggested experiments -- 1.6.1 Code for gate-level greater-than circuit -- 1.6.2 Code for gate-level binary decoder -- 2 Overview of FPGA and EDA software -- 2.1 Introduction -- 2.2 FPGA -- 2.2.1 Overview of a general FPGA device -- 2.2.2 Overview of the Xilinx Spartan-3 devices -- 2.3 Overview of the Digilent S3 board -- 2.4 Development flow -- 2.5 Overview of the Xilinx ISE project navigator -- 2.6 Short tutorial on ISE project navigator -- 2.6.1 Create the design project and HDL codes -- 2.6.2 Create a testbench and perform the RTL simulation -- 2.6.3 Add a constraint file and synthesize and implement the code -- 2.6.4 Generate and download the configuration file to an FPGA device -- 2.7 Short tutorial on the ModelSim HDL simulator -- 2.8 Bibliographic notes -- 2.9 Suggested experiments -- 2.9.1 Gate-level greater-than circuit -- 2.9.2 Gate-level binary decoder -- 3 RT-level combinational circuit -- 3.1 Introduction -- 3.2 RT-level components -- 3.2.1 Relational operators -- 3.2.2 Arithmetic operators -- 3.2.3 Other synthesis-related VHDL constructs -- 3.2.4 Summary -- 3.3 Routing circuit with concurrent assignment statements -- 3.3.1 Conditional signal assignment statement -- 3.3.2 Selected signal assignment statement -- 3.4 Modeling with a process -- 3.4.1 Process -- 3.4.2 Sequential signal assignment statement -- 3.5 Routing circuit with if and case statements.

3.5.1 If statement -- 3.5.2 Case statement -- 3.5.3 Comparison to concurrent statements -- 3.5.4 Unintended memory -- 3.6 Constants and generics -- 3.6.1 Constants -- 3.6.2 Generics -- 3.7 Design examples -- 3.7.1 Hexadecimal digit to seven-segment LED decoder -- 3.7.2 Sign-magnitude adder -- 3.7.3 Barrel shifter -- 3.7.4 Simplified floating-point adder -- 3.8 Bibliographic notes -- 3.9 Suggested experiments -- 3.9.1 Multi-function barrel shifter -- 3.9.2 Dual-priority encoder -- 3.9.3 BCD incrementor -- 3.9.4 Floating-point greater-than circuit -- 3.9.5 Floating-point and signed integer conversion circuit -- 3.9.6 Enhanced floating-point adder -- 4 Regular Sequential Circuit -- 4.1 Introduction -- 4.1.1 D FF and register -- 4.1.2 Synchronous system -- 4.1.3 Code development -- 4.2 HDL code of the FF and register -- 4.2.1 D FF -- 4.2.2 Register -- 4.2.3 Register file -- 4.2.4 Storage components in a Spartan-3 device Xilinx specific -- 4.3 Simple design examples -- 4.3.1 Shift register -- 4.3.2 Binary counter and variant -- 4.4 Testbench for sequential circuits -- 4.5 Case study -- 4.5.1 LED time-multiplexing circuit -- 4.5.2 Stopwatch -- 4.5.3 FIFO buffer -- 4.6 Bibliographic notes -- 4.7 Suggested experiments -- 4.7.1 Programmable square wave generator -- 4.7.2 PWM and LED dimmer -- 4.7.3 Rotating square circuit -- 4.7.4 Heartbeat circuit -- 4.7.5 Rotating LED banner circuit -- 4.7.6 Enhanced stopwatch -- 4.7.7 Stack -- 5 FSM -- 5.1 Introduction -- 5.1.1 Mealy and Moore outputs -- 5.1.2 FSM representation -- 5.2 FSM code development -- 5.3 Design examples -- 5.3.1 Rising-edge detector -- 5.3.2 Debouncing circuit -- 5.3.3 Testing circuit -- 5.4 Bibliographic notes -- 5.5 Suggested experiments -- 5.5.1 Dual-edge detector -- 5.5.2 Alternative debouncing circuit -- 5.5.3 Parking lot occupancy counter -- 6 FSMD -- 6.1 Introduction.

6.1.1 Single RT operation -- 6.1.2 ASMD chart -- 6.1.3 Decision box with a register -- 6.2 Code development of an FSMD -- 6.2.1 Debouncing circuit based on RT methodology -- 6.2.2 Code with explicit data path components -- 6.2.3 Code with implicit data path components -- 6.2.4 Comparison -- 6.2.5 Testing circuit -- 6.3 Design examples -- 6.3.1 Fibonacci number circuit -- 6.3.2 Division circuit -- 6.3.3 Binary-to-BCD conversion circuit -- 6.3.4 Period counter -- 6.3.5 Accurate low-frequency counter -- 6.4 Bibliographic notes -- 6.5 Suggested experiments -- 6.5.1 Alternative debouncing circuit -- 6.5.2 BCD-to-binary conversion circuit -- 6.5.3 Fibonacci circuit with BCD I/O: design approach 1 -- 6.5.4 Fibonacci circuit with BCD I/O: design approach 2 -- 6.5.5 Auto-scaled low-frequency counter -- 6.5.6 Reaction timer -- 6.5.7 Babbage difference engine emulation circuit -- PART II I/O MODULES -- 7 UART -- 7.1 Introduction -- 7.2 UART receiving subsystem -- 7.2.1 Oversampling procedure -- 7.2.2 Baud rate generator -- 7.2.3 UART receiver -- 7.2.4 Interface circuit -- 7.3 UART transmitting subsystem -- 7.4 Overall UART system -- 7.4.1 Complete UART core -- 7.4.2 UART verification configuration -- 7.5 Customizing a UART -- 7.6 Bibliographic notes -- 7.7 Suggested experiments -- 7.7.1 Full-featured UART -- 7.7.2 UART with an automatic baud rate detection circuit -- 7.7.3 UART with an automatic baud rate and parity detection circuit -- 7.7.4 UART-controlled stopwatch -- 7.7.5 UART-controlled rotating LED banner -- 8 PS2 Keyboard -- 8.1 Introduction -- 8.2 PS2 receiving subsystem -- 8.2.1 Physical interface of a PS2 port -- 8.2.2 Device-to-host communication protocol -- 8.2.3 Design and code -- 8.3 PS2 keyboard scan code -- 8.3.1 Overview of the scan code -- 8.3.2 Scan code monitor circuit -- 8.4 PS2 keyboard interface circuit -- 8.4.1 Basic design and HDL code.

8.4.2 Verification circuit -- 8.5 Bibliographic notes -- 8.6 Suggested experiments -- 8.6.1 Alternative keyboard interface I -- 8.6.2 Alternative keyboard interface II -- 8.6.3 PS2 receiving subsystem with watchdog timer -- 8.6.4 Keyboard-controlled stopwatch -- 8.6.5 Keyboard-controlled rotating LED banner -- 9 PS2 Mouse -- 9.1 Introduction -- 9.2 PS2 mouse protocol -- 9.2.1 Basic operation -- 9.2.2 Basic initialization procedure -- 9.3 PS2 transmitting subsystem -- 9.3.1 Host-to-PS2-device communication protocol -- 9.3.2 Design and code -- 9.4 Bidirectional PS2 interface -- 9.4.1 Basic design and code -- 9.4.2 Verification circuit -- 9.5 PS2 mouse interface -- 9.5.1 Basic design -- 9.5.2 Testing circuit -- 9.6 Bibliographic notes -- 9.7 Suggested experiments -- 9.7.1 Keyboard control circuit -- 9.7.2 Enhanced mouse interface -- 9.7.3 Mouse-controlled seven-segment LED display -- 10 External SRAM -- 10.1 Introduction -- 10.2 Specification of the IS61LV25616AL SRAM -- 10.2.1 Block diagram and I/O signals -- 10.2.2 Timing parameters -- 10.3 Basic memory controller -- 10.3.1 Block diagram -- 10.3.2 Timing requirement -- 10.3.3 Register file versus SRAM -- 10.4 A safe design -- 10.4.1 ASMD chart -- 10.4.2 Timing analysis -- 10.4.3 HDL implementation -- 10.4.4 Basic testing circuit -- 10.4.5 Comprehensive SRAM testing circuit -- 10.5 More aggressive design -- 10.5.1 Timing issues -- 10.5.2 Alternative design I -- 10.5.3 Alternative design II -- 10.5.4 Alternative design III -- 10.5.5 Advanced FPGA features Xilinx specific -- 10.6 Bibliographic notes -- 10.7 Suggested experiments -- 10.7.1 Memory with a 512K-by-16 configuration -- 10.7.2 Memory with a lM-by-8 configuration -- 10.7.3 Memory with an 8M-by-l configuration -- 10.7.4 Expanded memory testing circuit -- 10.7.5 Memory controller and testing circuit for alternative design I.

10.7.6 Memory controller and testing circuit for alternative design II -- 10.7.7 Memory controller and testing circuit for alternative design III -- 10.7.8 Memory controller with DCM -- 10.7.9 High-performance memory controller -- 11 Xilinx Spartan-3 Specific Memory -- 11.1 Introduction -- 11.2 Embedded memory of Spartan-3 device -- 11.2.1 Overview -- 11.2.2 Comparison -- 11.3 Method to incorporate memory modules -- 11.3.1 Memory module via HDL component instantiation -- 11.3.2 Memory module via Core Generator -- 11.3.3 Memory module via HDL inference -- 11.4 HDL templates for memory inference -- 11.4.1 Single-port RAM -- 11.4.2 Dual-port RAM -- 11.4.3 ROM -- 11.5 Bibliographic notes -- 11.6 Suggested experiments -- 11.6.1 Block-RAM-based FIFO -- 11.6.2 Block-RAM-based stack -- 11.6.3 ROM-based sign-magnitude adder -- 11.6.4 ROM based sin(x) function -- 11.6.5 ROM-based sin(x) and cos(x) functions -- 12 VGA controller I: graphic -- 12.1 Introduction -- 12.1.1 Basic operation of a CRT -- 12.1.2 VGA port of the S3 board -- 12.1.3 Video controller -- 12.2 VGA synchronization -- 12.2.1 Horizontal synchronization -- 12.2.2 Vertical synchronization -- 12.2.3 Timing calculation of VGA synchronization signals -- 12.2.4 HDL implementation -- 12.2.5 Testing circuit -- 12.3 Overview of the pixel generation circuit -- 12.4 Graphic generation with an object-mapped scheme -- 12.4.1 Rectangular objects -- 12.4.2 Non-rectangular object -- 12.4.3 Animated object -- 12.5 Graphic generation with a bit-mapped scheme -- 12.5.1 Dual-port RAM implementation -- 12.5.2 Single-port RAM implementation -- 12.6 Bibliographic notes -- 12.7 Suggested experiments -- 12.7.1 VGA test pattern generator -- 12.7.2 SVGA mode synchronization circuit -- 12.7.3 Visible screen adjustment circuit -- 12.7.4 Ball-in-a-box circuit -- 12.7.5 Two-balls-in-a-box circuit.

12.7.6 Two-player pong game.