Phase-Locked Loop Engineering Handbook for Integrated Circuits -- Contents vii -- Preface xiii -- Acknowledgments xxi -- Chapter 1 Getting Started with PLLs 1 -- 1.1 Definition and Operation 1 -- 1.2 Phase-Lock Loop Literature 5 -- 1.3 Loop Classifications 7 -- 1.4 Example Applications 7 -- Questions 12 -- References 13 -- Chapter 2 System Analysis 15 -- 2.1 VCO Mathematical Description 15 -- 2.2 Phase Detector Mathematical Relationship 16 -- 2.3 PLL Transfer Function and Control-Systems Theory 19 -- 2.4 Error Tracking 23 -- 2.5 Type 2, Second-Order Active Loop-to-Servo Terminology 24 -- 2.6 Loop Stability: Bode Plot Analysis 26 -- 2.7 Loop Stability: Root-Locus Analysis 28 -- 2.8 Charge Pump Synthesis Example of Loop-Component Values 30 -- 2.9 Summary 32 -- Questions 33 -- References 33 -- Chapter 3 System Requirements 35 -- 3.1 Noise Basics 35 -- 3.2 Phase-Noise and Oscillator Theory 53 -- 3.3 Jitter in PLLs 82 -- 3.4 Time-Domain Solution 96 -- 3.5 Acquisition of Lock 112 -- 3.6 Spurious Signals 123 -- 3.7 Summary 154 -- Questions 155 -- References 159 -- Appendix 3A: Single-Ended Explanation of Offset Currents 161 -- Chapter 4 Components, Part 1-Dividers and Oscillators 163 -- 4.1 Dividers 163 -- 4.2 Voltage-Controlled Oscillators 181 -- 4.3 Reference Oscillators 216 -- 4.4 Summary 231 -- Questions 232 -- References 233 -- Chapter 5 Components, Part 2-Detectors and Other Circuits 235 -- 5.1 Phase Detectors 235 -- 5.2 Lock Detection 268 -- 5.3 Acquisition Aids 275 -- 5.4 Charge Pumps 280 -- 5.5 Design Considerations for Opamps in a PLL 286 -- 5.6 Differences Between Charge Pump and Operational Amplifier Compensation 297 -- 5.7 Summary 302 -- Questions 304 -- References 306 -- Chapter 6 Loop-Compensation Synthesis Revisited 307 -- 6.1 Ranking Requirements for PLLs 308 -- 6.2 Loop-Component Synthesis 313.

6.3 Active Compensation and Maximum Capacitor Value 319 -- 6.4 Sampling-Delay Synthesis 321 -- 6.5 Fast Switching Time 330 -- 6.6 Minimum Bandwidth of a PLL 332 -- 6.7 Maximum-Divide-Ratio Example for Loop-Component Synthesis 337 -- 6.8 Optimum PLL Design for Low-Phase-Noise Performance 341 -- 6.9 Summary 349 -- Questions 350 -- References 352 -- Chapter 7 Test and Measurement 353 -- 7.1 Hold-In Range, Lock Range, and Spurious Signals 354 -- 7.2 Switching Time 356 -- 7.3 Closed-Loop Bandwidth 358 -- 7.4 Measurement of Phase Noise 359 -- 7.5 Testing for Jitter 377 -- 7.6 Noise Immunity to Injected Signals 388 -- 7.7 Power-On Switching Time 390 -- 7.8 Oscillator Open-Loop Test 391 -- 7.9 Test Equipment 393 -- 7.10 Troubleshooting PLLs 397 -- Questions 401 -- References 403 -- Chapater 8 Simulation 405 -- 8.1 Transistor Level 405 -- 8.2 Behavioral Modeling of PLL with PSPICE 412 -- 8.3 Difference-Equation Modeling of PLLs 421 -- Questions 443 -- References 444 -- Chapter 9 Applications and Extensions 445 -- 9.1 Design Trade-Offs in Frequency Generation with PLLs 445 -- 9.2 Clock Recovery 475 -- 9.3 Effect of Phase Noise on A/D Converters 506 -- 9.4 All-Digital PLLs 516 -- 9.5 Summary 526 -- Questions 527 -- References 527 -- Appendix A Letter Symbols 529 -- Appendix B Glossary 533 -- About the Author 541 -- Index 543.