FPGA Prototyping by Verilog Examples -- CONTENTS -- Preface -- Acknowledgments -- PART I BASIC DIGITAL CIRCUITS -- 1 Gate-level combinational circuit -- 1.1 Introduction -- 1.2 General description -- 1.3 Basic lexical elements and data types -- 1.3.1 Lexical elements -- 1.4 Data types -- 1.4.1 Four-value system -- 1.4.2 Data type groups -- 1.4.3 Number representation -- 1.4.4 Operators -- 1.5 Program skeleton -- 1.5.1 Port declaration -- 1 5.2 Program body -- 1.5.3 Signal declaration -- 1.5.4 Another example -- 1.6 Structural description -- 1.7 Testbench -- 1.8 Bibliographic notes -- 1.9 Suggested experiments -- 1.9.1 Code for gate-level greater-than circuit -- 1.9.2 Code for gate-level binary decoder -- 2 Overview of FPGA and EDA software -- 2.1 Introduction -- 2.2 FPGA -- 2.2.1 Overview of a general FPGA device -- 2.2.2 Overview of the Xilinx Spartan-3 devices -- 2.3 Overview of the Digilent S3 board -- 2.4 Development flow -- 2.5 Overview of the Xilinx ISE project navigator -- 2.6 Short tutorial on ISE project navigator -- 2.6.1 Create the design project and HDL codes -- 2.6.2 Create a testbench and perform the RTL simulation -- 2.6.3 Add a constraint file and synthesize and implement the code -- 2.6.4 Generate and download the configuration file to an FPGA device -- 2.7 Short tutorial on the ModelSim HDL simulator -- 2.8 Bibliographic notes -- 2.9 Suggested experiments -- 2.9.1 Gate-level greater-than circuit -- 2.9.2 Gate-level binary decoder -- 3 RT-level combinationaI circuit -- 3.1 Introduction -- 3.2 Operators -- 3.2.1 Arithmetic operators -- 3.2.2 Shift operators -- 3.2.3 Relational and equality operators -- 3.2.4 Bitwise, reduction, and logical operators -- 3.2.5 Concatenation and replication operators -- 3.2.6 Conditional operators -- 3.2.7 Operator precedence -- 3.2.8 Expression bit-length adjustment.

3.2.9 Synthesis of z and x values -- 3.3 Always block for a combinational circuit -- 3.3.1 Basic syntax and behavior -- 3.3.2 Procedural assignment -- 3.3.3 Variable data types -- 3.3.4 Simple examples -- 3.4 If statement -- 3.4.1 Syntax -- 3.4.2 Examples -- 3.5 Case statement -- 3.5.1 Syntax -- 3.5.2 Examples -- 3.5.3 The casez and casex statements -- 3.5.4 The full case and parallel case -- 3.6 Routing structure of conditional control constructs -- 3.6.1 Priority routing network -- 3.6.2 Multiplexing network -- 3.7 General coding guidelines for an always block -- 3.7.1 Common errors in combinational circuit codes -- 3.7.2 Guidelines -- 3.8 Parameter and constant -- 3.8.1 Constant -- 3.8.2 Parameter -- 3.8.3 Use of parameters in Verilog-1995 -- 3.9 Design examples -- 3.9.1 Hexadecimal digit to seven-segment LED decoder -- 3.9.2 Sign-magnitude adder -- 3.9.3 Barrel shifter -- 3.9.4 Simplified floating-point adder -- 3.10 Bibliographic notes -- 3.11 Suggested experiments -- 3.11.1 Multifunction barrel shifter -- 3.11.2 Dual-priority encoder -- 3.11.3 BCD incrementor -- 3.11.4 Floating-point greater-than circuit -- 3.11.5 Floating-point and signed integer conversion circuit -- 3.11.6 Enhanced floating-point adder -- 4 Regular Sequential Circuit -- 4.1 Introduction -- 4.1.1 D FF and register -- 4.1.2 Synchronous system -- 4.1.3 Code development -- 4.2 HDL code of the FF and register -- 4.2.1 D FF -- 4.2.2 Register -- 4.2.3 Register file -- 4.2.4 Storage components in a Spartan-3 deviceXilinx specific -- 4.3 Simple design examples -- 4.3.1 Shift register -- 4.3.2 Binary counter and variant -- 4.4 Testbench for sequential circuits -- 4.5 Case study -- 4.5.1 LED time-multiplexing circuit -- 4.5.2 Stopwatch -- 4.5.3 FIFO buffer -- 4.6 Bibliographic notes -- 4.7 Suggested experiments -- 4.7.1 Programmable square-wave generator -- 4.7.2 PWM and LED dimmer.

4.7.3 Rotating square circuit -- 4.7.4 Heartbeat circuit -- 4.7.5 Rotating LED banner circuit -- 4.7.6 Enhanced stopwatch -- 4.7.7 Stack -- 5 FSM -- 5.1 Introduction -- 5.1.1 Mealy and Moore outputs -- 5.1.2 FSM representation -- 5.2 FSM code development -- 5.3 Design examples -- 5.3.1 Rising-edge detector -- 5.3.2 Debouncing circuit -- 5.3.3 Testing circuit -- 5.4 Bibliographic notes -- 5.5 Suggested experiments -- 5.5.1 Dual-edge detector -- 5.5.2 Alternative debouncing circuit -- 5.5.3 Parking lot occupancy counter -- 6 FSMD -- 6.1 Introduction -- 6.1.1 Single RT operation -- 6.1.2 ASMD chart -- 6.1.3 Decision box with a register -- 6.2 Code development of an FSMD -- 6.2.1 Debouncing circuit based on RT methodology -- 6.2.2 Code with explicit data path components -- 6.2.3 Code with implicit data path components -- 6.2.4 Comparison -- 6.2.5 Testing circuit -- 6.3 Design examples -- 6.3.1 Fibonacci number circuit -- 6.3.2 Division circuit -- 6.3.3 Binary-to-BCD conversion circuit -- 6.3.4 Period counter -- 6.3.5 Accurate low-frequency counter -- 6.4 Bibliographic notes -- 6.5 Suggested experiments -- 6.5.1 Alternative debouncing circuit -- 6.5.2 BCD-to-binary conversion circuit -- 6.5.3 Fibonacci circuit with BCD I/O: design approach I -- 6.5.4 Fibonacci circuit with BCD I/O: design approach 2 -- 6.5.5 Auto-scaled low-frequency counter -- 6.5.6 Reaction timer -- 6.5.7 Babbage difference engine emulation circuit -- 7 Selected Topics of Verilog -- 7.1 Blocking versus nonblocking assignment -- 7.1.1 Overview -- 7.1.2 Combinational circuit -- 7.1.3 Memory element -- 7.1.4 Sequential circuit with mixed blocking and nonblocking assignments -- 7.2 Alternative coding style for sequential circuit -- 7.2.1 Binary counter -- 7.2.2 FSM -- 7.2.3 FSMD -- 7.2.4 Summary -- 7.3 Use of the signed data type -- 7.3.1 Overview -- 7.3.2 Signed number in Verilog-1995.

7.3.3 Signed number in Verilog-2001 -- 7.4 Use of function in synthesis -- 7.4.1 Overview -- 7.4.2 Examples -- 7.5 Additional constructs for testbench development -- 7.5.1 Always block and initial block -- 7.5.2 Procedural statements -- 7.5.3 Timing control -- 7.5.4 Delay control -- 7.5.5 Event control -- 7.5.6 Wait statement -- 7.5.7 Timescale directive -- 7.5.8 System functions and tasks -- 7.5.9 User-defined functions and tasks -- 7.5.10 Example of a comprehensive testbench -- 7.6 Bibliographic notes -- 7.7 Suggested experiments -- 7.7.1 Shift register with blocking and nonblocking assignments -- 7.7.2 Alternative coding style for BCD counter -- 7.7.3 Alternative coding style for FIFO buffer -- 7.7.4 Alternative coding style for Fibonacci circuit -- 7.7.5 Dual-mode comparator -- 7.7.6 Enhanced binary counter monitor -- 7.7.7 Testbench for FIFO buffer -- PART II I/O MODULES -- 8 UART -- 8.1 Introduction -- 8.2 UART receiving subsystem -- 8.2.1 Oversampling procedure -- 8.2.2 Baud rate generator -- 8.2.3 UART receiver -- 8.2.4 Interface circuit -- 8.3 UART transmitting subsystem -- 8.4 Overall UART system -- 8.4.1 Complete UART core -- 8.4.2 UART verification configuration -- 8.5 Customizing a UART -- 8.6 Bibliographic notes -- 8.7 Suggested experiments -- 8.7.1 Full-featured UART -- 8.7.2 UART with an automatic baud rate detection circuit -- 8.7.3 UART with an automatic baud rate and parity detection circuit -- 8.7.4 UART-controlled stopwatch -- 8.7.5 UART-controlled rotating LED banner -- 9 PS2 Keyboard -- 9.1 Introduction -- 9.2 PS2 receiving subsystem -- 9.2.1 Physical interface of a PS2 port -- 9.2.2 Device-to-host communication protocol -- 9.2.3 Design and code -- 9.3 PS2 keyboard scan code -- 9.3.1 Overview of the scan code -- 9.3.2 Scan code monitor circuit -- 9.4 PS2 keyboard interface circuit -- 9.4.1 Basic design and HDL code.

9.4.2 Verification circuit -- 9.5 Bibliographic notes -- 9.6 Suggested experiments -- 9.6.1 Alternative keyboard interface I -- 9.6.2 Alternative keyboard interface II -- 9.6.3 PS2 receiving subsystem with watchdog timer -- 9.6.4 Keyboard-controlled stopwatch -- 9.6.5 Keyboard-controlled rotating LED banner -- 10 PS2 Mouse -- 10.1 Introduction -- 10.2 PS2 mouse protocol -- 10.2.1 Basic operation -- 10.2.2 Basic initialization procedure -- 10.3 PS2 transmitting subsystem -- 10.3.1 Host-to-PS2-device communication protocol -- 10.3.2 Design and code -- 10.4 Bidirectional PS2 interface -- 10.4.1 Basic design and code -- 10.4.2 Verification circuit -- 10.5 PS2 mouse interface -- 10.5.1 Basic design -- 10.5.2 Testing circuit -- 10.6 Bibliographic notes -- 10.7 Suggested experiments -- 10.7.1 Keyboard control circuit -- 10.7.2 Enhanced mouse interface -- 10.7.3 Mouse-controlled seven-segment LED display -- 11 External SRAM -- 11.1 Introduction -- 11.2 Specification of the IS61LV25616AL SRAM -- 11.2.1 Block diagram and I/O signals -- 11.2.2 Timing parameters -- 11.3 Basic memory controller -- 11.3.1 Block diagram -- 11.3.2 Timing requirement -- 11.3.3 Register file versus SRAM -- 11.4 A safe design -- 11.4.1 ASMD chart -- 11.4.2 Timing analysis -- 11.4.3 HDL implementation -- 11.4.4 Basic testing circuit -- 11.4.5 Comprehensive SRAM testing circuit -- 11.5 More aggressive design -- 11.5.1 Timing issues -- 11. 5.2 Alternative design I -- 11. 5.3 Alternative design II -- 11. 5.4 Alternative design III -- 11. 5.5 Advanced FPGA features Xilinx specific -- 11.6 Bibliographic notes -- 11.7 Suggested experiments -- 11.7.1 Memory with a 512K-by-16 configuration -- 11.7.2 Memory with a 1M-by-8 configuration -- 11.7.3 Memory with an 8M-by-1 configuration -- 11.7.4 Expanded memory testing circuit -- 11.7.5 Memory controller and testing circuit for alternative design I.

11.7.6 Memory controller and testing circuit for alternative design II.