Digital Design of Signal Processing Systems : A Practical Approach.
Title:
Digital Design of Signal Processing Systems : A Practical Approach.
Author:
Khan, Shoab Ahmed.
ISBN:
9781119956389
Personal Author:
Edition:
1st ed.
Physical Description:
1 online resource (698 pages)
Contents:
DIGITAL DESIGN OF SIGNAL PROCESSING SYSTEMS: A PRACTICAL APPROACH -- Contents -- Preface -- Acknowledgments -- 1 Overview -- 1.1 Introduction -- 1.2 Fueling the Innovation: Moore's Law -- 1.3 Digital Systems -- 1.3.1 Principles -- 1.3.2 Multi-core Systems -- 1.3.3 NoC-based MPSoC -- 1.4 Examples of Digital Systems -- 1.4.1 Digital Receiver for a Voice Communication System -- 1.4.2 The Backplane of a Router -- 1.5 Components of the Digital Design Process -- 1.5.1 Design -- 1.5.2 Implementation -- 1.5.3 Verification -- 1.6 Competing Objectives in Digital Design -- 1.7 Synchronous Digital Hardware Systems -- 1.8 Design Strategies -- 1.8.1 Example of Design Partitioning -- 1.8.2 NoC-based SoC for Carrier-class VoIP Media Gateway -- 1.8.3 Design Flow Migration -- References -- 2 Using a Hardware Description Language -- 2.1 Overview -- 2.2 About Verilog -- 2.2.1 History -- 2.2.2 What is Verilog? -- 2.3 System Design Flow -- 2.4 Logic Synthesis -- 2.5 Using the Verilog HDL -- 2.5.1 Modules -- 2.5.2 Design Partitioning -- 2.5.3 Hierarchical Design -- 2.5.4 Logic Values -- 2.5.5 Data Types -- 2.5.6 Variable Declaration -- 2.5.7 Constants -- 2.6 Four Levels of Abstraction -- 2.6.1 Switch Level -- 2.6.2 Gate Level or Structural Modeling -- 2.6.3 Dataflow Level -- 2.6.4 Behavioral Level -- 2.6.5 Verilog Tasks -- 2.6.6 Verilog Functions -- 2.6.7 Signed Arithmetic -- 2.7 Verification in Hardware Design -- 2.7.1 Introduction to Verification -- 2.7.2 Approaches to Testing a Digital Design -- 2.7.3 Levels of Testing in the Development Cycle -- 2.7.4 Methods for Generating Test Cases -- 2.7.5 Transaction-level Modeling -- 2.8 Example of a Verification Setup -- 2.9 SystemVerilog -- 2.9.1 Data Types -- 2.9.2 Module Instantiation and Port Listing -- 2.9.3 Constructs of the C/C++ Type -- 2.9.4 for and do-while Loops -- 2.9.5 The always Procedural Block.
2.9.6 The final Procedural Block -- 2.9.7 The unique and priority Case Statements -- 2.9.8 Nested Modules -- 2.9.9 Functions and Tasks -- 2.9.10 The Interface -- 2.9.11 Classes -- 2.9.12 Direct Programming Interface (DPI) -- 2.9.13 Assertion -- 2.9.14 Packages -- 2.9.15 Randomization -- 2.9.16 Coverage -- Exercises -- References -- 3 System Design Flow and Fixed-point Arithmetic -- 3.1 Overview -- 3.2 System Design Flow -- 3.2.1 Principles -- 3.2.2 Example: Requirements and Specifications of a UHF Software-defined Radio -- 3.2.3 Coding Guidelines for High-level Behavioral Description -- 3.2.4 Fixed-point versus Floating-point Hardware -- 3.3 Representation of Numbers -- 3.3.1 Types of Representation -- 3.3.2 Two's Complement Representation -- 3.3.3 Computing Two's Complement of a Signed Number -- 3.3.4 Scaling -- 3.4 Floating-point Format -- 3.4.1 Normalized and Denormalized Values -- 3.4.2 Floating-point Arithmetic Addition -- 3.4.3 Floating-point Multiplication -- 3.5 Qn.m Format for Fixed-point Arithmetic -- 3.5.1 Introducing Qn.m -- 3.5.2 Floating-point to Fixed-point Conversion of Numbers -- 3.5.3 Addition in Q Format -- 3.5.4 Multiplication in Q Format -- 3.5.5 Bit Growth in Fixed-point Arithmetic -- 3.5.6 Overflow and Saturation -- 3.5.7 Two's Complement Intermediate Overflow Property -- 3.5.8 Corner Cases -- 3.5.9 Code Conversion and Checking the Corner Case -- 3.5.10 Rounding the Product in Fixed-point Multiplication -- 3.5.11 MATLAB® Support for Fixed-point Arithmetic -- 3.5.12 SystemC Support for Fixed-point Arithmetic -- 3.6 Floating-point to Fixed-point Conversion -- 3.7 Block Floating-point Format -- 3.8 Forms of Digital Filter -- 3.8.1 Infinite Impulse Response Filter -- 3.8.2 Quantization of IIR Filter Coefficients -- 3.8.3 Coefficient Quantization Analysis of a Second-order Section -- 3.8.4 Folded FIR Filters.
3.8.5 Coefficient Quantization of an FIR Filter -- Exercises -- References -- 4 Mapping on Fully Dedicated Architecture -- 4.1 Introduction -- 4.2 Discrete Real-time Systems -- 4.3 Synchronous Digital Hardware Systems -- 4.4 Kahn Process Networks -- 4.4.1 Introduction to KPN -- 4.4.2 KPN for Modeling Streaming Applications -- 4.4.3 Limitations of KPN -- 4.4.4 Modified KPN and MPSoC -- 4.4.5 Case Study: GMSK Communication Transmitter -- 4.5 Methods of Representing DSP Systems -- 4.5.1 Introduction -- 4.5.2 Block Diagram -- 4.5.3 Signal Flow Graph -- 4.5.4 Dataflow Graph or Data Dependency Graph -- 4.5.5 Self-timed Firing -- 4.5.6 Single-rate and Multi-rate SDFGs -- 4.5.7 Homogeneous SDFG -- 4.5.8 Cyclo-static DFG -- 4.5.9 Multi-dimensional Arrayed Dataflow Graphs -- 4.5.10 Control Flow Graphs -- 4.5.11 Finite State Machine -- 4.5.12 Transformations on a Dataflow Graph -- 4.5.13 Dataflow Interchange Format (DIF) Language -- 4.6 Performance Measures -- 4.6.1 Iteration Period -- 4.6.2 Sampling Period and Throughput -- 4.6.3 Latency -- 4.6.4 Power Dissipation -- 4.7 Fully Dedicated Architecture -- 4.7.1 The Design Space -- 4.7.2 Pipelining -- 4.7.3 Selecting Basic Building Blocks -- 4.7.4 Extending the Concept of One-to-one Mapping -- 4.8 DFG to HW Synthesis -- 4.8.1 Mapping a Multi-rate DFG in Hardware -- 4.8.2 Centralized Controller for DFG Realization -- Exercises -- References -- 5 Design Options for Basic Building Blocks -- 5.1 Introduction -- 5.2 Embedded Processors and Arithmetic Units in FPGAs -- 5.3 Instantiation of Embedded Blocks -- 5.3.1 Example of Optimized Mapping -- 5.3.2 Design Optimization for the Target Technology -- 5.4 Basic Building Blocks: Introduction -- 5.5 Adders -- 5.5.1 Overview -- 5.5.2 Half Adders and Full Adders -- 5.5.3 Ripple Carry Adder -- 5.5.4 Fast Adders -- 5.5.5 Carry Look-ahead Adder.
5.5.6 Hybrid Ripple Carry and Carry Look-ahead Adder -- 5.5.7 Binary Carry Look-ahead Adder -- 5.5.8 Carry Skip Adder -- 5.5.9 Conditional Sum Adder -- 5.5.10 Carry Select Adder -- 5.5.11 Using Hybrid Adders -- 5.6 Barrel Shifter -- 5.7 Carry Save Adders and Compressors -- 5.7.1 Carry Save Adders -- 5.7.2 Compression Trees -- 5.7.3 Dot Notation -- 5.8 Parallel Multipliers -- 5.8.1 Introduction -- 5.8.2 Partial Product Generation -- 5.8.3 Partial Product Reduction -- 5.8.4 A Decomposed Multiplier -- 5.8.5 Optimized Compressors -- 5.8.6 Single- and Multiple-column Counters -- 5.9 Two's Complement Signed Multiplier -- 5.9.1 Basics -- 5.9.2 Sign Extension Elimination -- 5.9.3 String Property -- 5.9.4 Modified Booth Recoding Multiplier -- 5.9.5 Modified Booth Recoded Multiplier in RTL Verilog -- 5.10 Compression Trees for Multi-operand Addition -- 5.11 Algorithm Transformations for CSA -- Exercises -- References -- 6 Multiplier-less Multiplication by Constants -- 6.1 Introduction -- 6.2 Canonic Signed Digit Representation -- 6.3 Minimum Signed Digit Representation -- 6.4 Multiplication by a Constant in a Signal Processing Algorithm -- 6.5 Optimized DFG Transformation -- 6.6 Fully Dedicated Architecture for Direct-form FIR Filter -- 6.6.1 Introduction -- 6.6.2 Example: Five-coefficient Filter -- 6.6.3 Transposed Direct-form FIR Filter -- 6.6.4 Example: TDF Architecture -- 6.6.5 Hybrid FIR Filter Structure -- 6.7 Complexity Reduction -- 6.7.1 Sub-graph Sharing -- 6.7.2 Common Sub-expression Elimination -- 6.7.3 Common Sub-expressions with Multiple Operands -- 6.8 Distributed Arithmetic -- 6.8.1 Basics -- 6.8.2 Example: FIR Filter Design -- 6.8.3 M-parallel Sub-filter-based Design -- 6.8.4 DA Implementation without Look-up Tables -- 6.9 FFT Architecture using FIR Filter Structure -- Exercises -- References.
7 Pipelining, Retiming, Look-ahead Transformation and Polyphase Decomposition -- 7.1 Introduction -- 7.2 Pipelining and Retiming -- 7.2.1 Basics -- 7.2.2 Cut-set Retiming -- 7.2.3 Retiming using the Delay Transfer Theorem -- 7.2.4 Pipelining and Retiming in a Feedforward System -- 7.2.5 Re-pipelining: Pipelining using Feedforward Cut-set -- 7.2.6 Cut-set Retiming of a Direct-form FIR Filter -- 7.2.7 Pipelining using the Delay Transfer Theorem -- 7.2.8 Pipelining Optimized DFG -- 7.2.9 Pipelining Carry Propagate Adder -- 7.2.10 Retiming Support in Synthesis Tools -- 7.2.11 Mathematical Formulation of Retiming -- 7.2.12 Minimizing the Number of Registers and Critical Path Delay -- 7.2.13 Retiming with Shannon Decomposition -- 7.2.14 Peripheral Retiming -- 7.3 Digital Design of Feedback Systems -- 7.3.1 Definitions -- 7.3.2 Cut-set Retiming for a Feedback System -- 7.3.3 Shannon Decomposition to Reduce the IPB -- 7.4 C-slow Retiming -- 7.4.1 Basics -- 7.4.2 C-slow for Block Processing -- 7.4.3 C-slow for FPGAs and Time-multiplexed Reconfigurable Design -- 7.4.4 C-slow for an Instruction Set Processor -- 7.5 Look-ahead Transformation for IIR filters -- 7.6 Look-ahead Transformation for Generalized IIR Filters -- 7.7 Polyphase Structure for Decimation andInterpolation Applications -- 7.8 IIR Filter for Decimation and Interpolation -- Exercises -- References -- 8 Unfolding and Foldingof Architectures -- 8.1 Introduction -- 8.2 Unfolding -- 8.3 Sampling Rate Considerations -- 8.3.1 Nyquist Sampling Theorem and Design Options -- 8.3.2 Software-defined Radio Architecture and Band-pass Sampling -- 8.3.3 A/D Converter Bandwidth and Band-pass Sampling -- 8.4 Unfolding Techniques -- 8.4.1 Loop Unrolling -- 8.4.2 Unfolding Transformation -- 8.4.3 Loop Unrolling for Mapping SW to HW -- 8.4.4 Unfolding to Maximize Use of a Compression Tree.
8.4.5 Unfolding for Effective Use of FPGA Resources.
Abstract:
Digital Design of Signal Processing Systems discusses a spectrum of architectures and methods for effective implementation of algorithms in hardware (HW). Encompassing all facets of the subject this book includes conversion of algorithms from floating-point to fixed-point format, parallel architectures for basic computational blocks, Verilog Hardware Description Language (HDL), SystemVerilog and coding guidelines for synthesis. The book also covers system level design of Multi Processor System on Chip (MPSoC); a consideration of different design methodologies including Network on Chip (NoC) and Kahn Process Network (KPN) based connectivity among processing elements. A special emphasis is placed on implementing streaming applications like a digital communication system in HW. Several novel architectures for implementing commonly used algorithms in signal processing are also revealed. With a comprehensive coverage of topics the book provides an appropriate mix of examples to illustrate the design methodology. Key Features: A practical guide to designing efficient digital systems, covering the complete spectrum of digital design from a digital signal processing perspective Provides a full account of HW building blocks and their architectures, while also elaborating effective use of embedded computational resources such as multipliers, adders and memories in FPGAs Covers a system level architecture using NoC and KPN for streaming applications, giving examples of structuring MATLAB code and its easy mapping in HW for these applications Explains state machine based and Micro-Program architectures with comprehensive case studies for mapping complex applications The techniques and examples discussed in this book are used in the award winning products from the Center for Advanced Research in Engineering (CARE). Software Defined Radio, 10 Gigabit VoIP
monitoring system and Digital Surveillance equipment has respectively won APICTA (Asia Pacific Information and Communication Alliance) awards in 2010 for their unique and effective designs.
Local Note:
Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2017. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries.
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