COMPUTER SYSTEM DESIGN -- CONTENTS -- PREFACE -- LIST OF ABBREVIATIONS AND ACRONYMS -- 1: Introduction to the Systems Approach -- 1.1 SYSTEM ARCHITECTURE: AN OVERVIEW -- 1.2 COMPONENTS OF THE SYSTEM: PROCESSORS, MEMORIES, AND INTERCONNECTS -- 1.3 HARDWARE AND SOFTWARE: PROGRAMMABILITY VERSUS PERFORMANCE -- 1.4 PROCESSOR ARCHITECTURES -- 1.4.1 Processor: A Functional View -- 1.4.2 Processor: An Architectural View -- 1.5 MEMORY AND ADDRESSING -- 1.5.1 SOC Memory Examples -- 1.5.2 Addressing: The Architecture of Memory -- 1.5.3 Memory for SOC Operating System -- 1.6 SYSTEM-LEVEL INTERCONNECTION -- 1.6.1 Bus-Based Approach -- 1.6.2 Network-on-Chip Approach -- 1.7 AN APPROACH FOR SOC DESIGN -- 1.7.1 Requirements and Specifications -- 1.7.2 Design Iteration -- 1.8 SYSTEM ARCHITECTURE AND COMPLEXITY -- 1.9 PRODUCT ECONOMICS AND IMPLICATIONS FOR SOC -- 1.9.1 Factors Affecting Product Costs -- 1.9.2 Modeling Product Economics and Technology Complexity: The Lesson for SOC -- 1.10 DEALING WITH DESIGN COMPLEXITY -- 1.10.1 Buying IP -- 1.10.2 Reconfiguration -- 1.11 CONCLUSIONS -- 1.12 PROBLEM SET -- 2: Chip Basics: Time, Area, Power, Reliability, and Configurability -- 2.1 INTRODUCTION -- 2.1.1 Design Trade-Offs -- 2.1.2 Requirements and Specifications -- 2.2 CYCLE TIME -- 2.2.1 Defining a Cycle -- 2.2.2 Optimum Pipeline -- 2.2.3 Performance -- 2.3 DIE AREA AND COST -- 2.3.1 Processor Area -- 2.3.2 Processor Subunits -- 2.4 IDEAL AND PRACTICAL SCALING -- 2.5 POWER -- 2.6 AREA-TIME-POWER TRADE-OFFS IN PROCESSOR DESIGN -- 2.6.1 Workstation Processor -- 2.6.2 Embedded Processor -- 2.7 RELIABILITY -- 2.7.1 Dealing with Physical Faults -- 2.7.2 Error Detection and Correction -- 2.7.3 Dealing with Manufacturing Faults -- 2.7.4 Memory and Function Scrubbing -- 2.8 CONFIGURABILITY -- 2.8.1 Why Reconfigurable Design? -- 2.8.2 Area Estimate of Reconfigurable Devices.

2.9 CONCLUSION -- 2.10 PROBLEM SET -- 3: Processors -- 3.1 INTRODUCTION -- 3.2 PROCESSOR SELECTION FOR SOC -- 3.2.1 Overview -- 3.2.2 Example: Soft Processors -- 3.2.3 Examples: Processor Core Selection -- 3.3 BASIC CONCEPTS IN PROCESSOR ARCHITECTURE -- 3.3.1 Instruction Set -- 3.3.2 Some Instruction Set Conventions -- 3.3.3 Branches -- 3.3.4 Interrupts and Exceptions -- 3.4 BASIC CONCEPTS IN PROCESSOR MICROARCHITECTURE -- 3.5 BASIC ELEMENTS IN INSTRUCTION HANDLING -- 3.5.1 The Instruction Decoder and Interlocks -- 3.5.2 Bypassing -- 3.5.3 Execution Unit -- 3.6 BUFFERS: MINIMIZING PIPELINE DELAYS -- 3.6.1 Mean Request Rate Buffers -- 3.6.2 Buffers Designed for a Fixed or Maximum Request Rate -- 3.7 BRANCHES: REDUCING THE COST OF BRANCHES -- 3.7.1 Branch Target Capture: Branch Target Buffers (BTBs) -- 3.7.2 Branch Prediction -- 3.8 MORE ROBUST PROCESSORS: VECTOR, VERY LONG INSTRUCTION WORD (VLIW), AND SUPERSCALAR -- 3.9 VECTOR PROCESSORS AND VECTOR INSTRUCTION EXTENSIONS -- 3.9.1 Vector Functional Units -- 3.10 VLIW PROCESSORS -- 3.11 SUPERSCALAR PROCESSORS -- 3.11.1 Data Dependencies -- 3.11.2 Detecting Instruction Concurrency -- 3.11.3 A Simple Implementation -- 3.11.4 Preserving State with Out-of-Order Execution -- 3.12 PROCESSOR EVOLUTION AND TWO EXAMPLES -- 3.12.1 Soft and Firm Processor Designs: The Processor as IP -- 3.12.2 High-Performance, Custom-Designed Processors -- 3.13 CONCLUSIONS -- 3.14 PROBLEM SET -- 4: Memory Design: System-on-Chip and Board-Based Systems -- 4.1 INTRODUCTION -- 4.2 OVERVIEW -- 4.2.1 SOC External Memory: Flash -- 4.2.2 SOC Internal Memory: Placement -- 4.2.3 The Size of Memory -- 4.3 SCRATCHPADS AND CACHE MEMORY -- 4.4 BASIC NOTIONS -- 4.5 CACHE ORGANIZATION -- 4.6 CACHE DATA -- 4.7 WRITE POLICIES -- 4.8 STRATEGIES FOR LINE REPLACEMENT AT MISS TIME -- 4.8.1 Fetching a Line -- 4.8.2 Line Replacement.

4.8.3 Cache Environment: Effects of System, Transactions, and Multiprogramming -- 4.9 OTHER TYPES OF CACHE -- 4.10 SPLIT I-AND D-CACHES AND THE EFFECT OF CODE DENSITY -- 4.11 MULTILEVEL CACHES -- 4.11.1 Limits on Cache Array Size -- 4.11.2 Evaluating Multilevel Caches -- 4.11.3 Logical Inclusion -- 4.12 VIRTUAL-TO-REAL TRANSLATION -- 4.13 SOC (ON-DIE) MEMORY SYSTEMS -- 4.14 BOARD-BASED (OFF-DIE) MEMORY SYSTEMS -- 4.15 SIMPLE DRAM AND THE MEMORY ARRAY -- 4.15.1 SDRAM and DDR SDRAM -- 4.15.2 Memory Buffers -- 4.16 MODELS OF SIMPLE PROCESSOR-MEMORY INTERACTION -- 4.16.1 Models of Multiple Simple Processors and Memory -- 4.16.2 The Strecker-Ravi Model -- 4.16.3 Interleaved Caches -- 4.17 CONCLUSIONS -- 4.18 PROBLEM SET -- 5: Interconnect -- 5.1 INTRODUCTION -- 5.2 OVERVIEW: INTERCONNECT ARCHITECTURES -- 5.3 BUS: BASIC ARCHITECTURE -- 5.3.1 Arbitration and Protocols -- 5.3.2 Bus Bridge -- 5.3.3 Physical Bus Structure -- 5.3.4 Bus Varieties -- 5.4 SOC STANDARD BUSES -- 5.4.1 AMBA -- 5.4.2 CoreConnect -- 5.4.3 Bus Interface Units: Bus Sockets and Bus Wrappers -- 5.5 ANALYTIC BUS MODELS -- 5.5.1 Contention and Shared Bus -- 5.5.2 Simple Bus Model: Without Resubmission -- 5.5.3 Bus Model with Request Resubmission -- 5.5.4 Using the Bus Model: Computing the Offered Occupancy -- 5.5.5 Effect of Bus Transactions and Contention Time -- 5.6 BEYOND THE BUS: NOC WITH SWITCH INTERCONNECTS -- 5.6.1 Static Networks -- 5.6.2 Dynamic Networks -- 5.7 SOME NOC SWITCH EXAMPLES -- 5.7.1 A 2-D Grid Example of Direct Networks -- 5.7.2 Asynchronous Crossbar Interconnect for Synchronous SOC (Dynamic Network) -- 5.7.3 Blocking versus Nonblocking -- 5.8 LAYERED ARCHITECTURE AND NETWORK INTERFACE UNIT -- 5.8.1 NOC Layered Architecture -- 5.8.2 NOC and NIU Example -- 5.8.3 Bus versus NOC -- 5.9 EVALUATING INTERCONNECT NETWORKS -- 5.9.1 Static versus Dynamic Networks.

5.9.2 Comparing Networks: Example -- 5.10 CONCLUSIONS -- 5.11 PROBLEM SET -- 6: Customization and Configurability -- 6.1 INTRODUCTION -- 6.2 ESTIMATING EFFECTIVENESS OF CUSTOMIZATION -- 6.3 SOC CUSTOMIZATION: AN OVERVIEW -- 6.4 CUSTOMIZING INSTRUCTION PROCESSORS -- 6.4.1 Processor Customization Approaches -- 6.4.2 Architecture Description -- 6.4.3 Identifying Custom Instructions Automatically -- 6.5 RECONFIGURABLE TECHNOLOGIES -- 6.5.1 Reconfigurable Functional Units (FUs) -- 6.5.2 Reconfigurable Interconnects -- 6.5.3 Software Configurable Processors -- 6.6 MAPPING DESIGNS ONTO RECONFIGURABLE DEVICES -- 6.7 INSTANCE-SPECIFIC DESIGN -- 6.8 CUSTOMIZABLE SOFT PROCESSOR: AN EXAMPLE -- 6.9 RECONFIGURATION -- 6.9.1 Reconfiguration Overhead Analysis -- 6.9.2 Trade-Off Analysis: Reconfigurable Parallelism -- 6.10 CONCLUSIONS -- 6.11 PROBLEM SET -- 7: Application Studies -- 7.1 INTRODUCTION -- 7.2 SOC DESIGN APPROACH -- 7.3 APPLICATION STUDY: AES -- 7.3.1 AES : Algorithm and Requirements -- 7.3.2 AES : Design and Evaluation -- 7.4 APPLICATION STUDY: 3-D GRAPHICS PROCESSORS -- 7.4.1 Analysis: Processing -- 7.4.2 Analysis: Interconnection -- 7.4.3 Prototyping -- 7.5 APPLICATION STUDY: IMAGE COMPRESSION -- 7.5.1 JPEG Compression -- 7.5.2 Example JPEG System for Digital Still Camera -- 7.6 APPLICATION STUDY: VIDEO COMPRESSION -- 7.6.1 MPEG and H.26X Video Compression: Requirements -- 7.6.2 H.264 Acceleration: Designs -- 7.7 FURTHER APPLICATION STUDIES -- 7.7.1 MP3 Audio Decoding -- 7.7.2 Software-Defined Radio with 802.16 -- 7.8 CONCLUSIONS -- 7.9 PROBLEM SET -- 8: What's Next: Challenges Ahead -- 8.1 INTRODUCTION -- 8.2 OVERVIEW -- 8.3 TECHNOLOGY -- 8.4 POWERING THE ASOC -- 8.5 THE SHAPE OF THE ASOC -- 8.6 COMPUTER MODULE AND MEMORY -- 8.7 RF OR LIGHT COMMUNICATIONS -- 8.7.1 Lasers -- 8.7.2 RF -- 8.7.3 Potential for Laser/RF Communications.

8.7.4 Networked ASOC -- 8.8 SENSING -- 8.8.1 Visual -- 8.8.2 Audio -- 8.9 MOTION, FLIGHT, AND THE FRUIT FLY -- 8.10 MOTIVATION -- 8.11 OVERVIEW -- 8.12 PRE-DEPLOYMENT -- 8.13 POST-DEPLOYMENT -- 8.13.1 Situation-Specific Optimization -- 8.13.2 Autonomous Optimization Control -- 8.14 ROADMAP AND CHALLENGES -- 8.15 SUMMARY -- APPENDIX: Tools for Processor Evaluation -- REFERENCES -- INDEX.