Organic Thin Film Transistor Integration -- Contents -- Preface -- Glossary -- 1 Introduction -- 1.1 Organic Electronics: History and Market Opportunities -- 1.1.1 Large-Area Displays -- 1.1.2 Rollable Displays -- 1.1.3 Radio Frequency Identification (RFID) Tag -- 1.1.4 Technological Challenges -- 1.1.4.1 Device Performance -- 1.1.4.2 Device Manufacture -- 1.1.5 Scope and Organization -- References -- 2 Organic Thin Film Transistor (OTFT) Overview -- 2.1 Organic Semiconductor Overview -- 2.1.1 Basic Properties -- 2.1.2 Charge Transport -- 2.1.3 Microstructure and Molecular Alignment -- 2.1.4 Material Development and Classifications -- 2.1.4.1 Small Molecules -- 2.1.4.2 Polymers -- 2.1.4.3 n-Type Semiconductors -- 2.1.5 Sensitivity to Environmental Influences -- 2.2 OTFT Operation and Characteristics -- 2.2.1 OTFT Parameter Extraction -- 2.2.2 Contact Resistance Extraction -- 2.2.3 Desirable OTFT Characteristics -- 2.3 OTFT Device Architecture -- 2.3.1 Top-Contact and Bottom-Contact OTFTs -- 2.3.2 Top-Gate, Bottom-Gate, and Dual-Gate OTFTs -- 2.4 OTFT Device Material Selection -- 2.4.1 Organic Semiconductor -- 2.4.2 Gate Dielectric -- 2.4.3 Electrodes/Contacts -- 2.4.4 Substrate -- 2.4.5 Encapsulation Strategies -- 2.5 Summary -- References -- 3 OTFT Integration Strategies -- 3.1 Technological Challenge in OTFT Integration -- 3.2 Overview of Processing and Fabrication Techniques -- 3.2.1 Deposition Methods for Organic Semiconductors -- 3.2.1.1 Vacuum Evaporation -- 3.2.1.2 Solution-Processed Deposition -- 3.2.2 Patterning by Shadow Mask -- 3.2.3 Patterning by Photolithography -- 3.2.3.1 Photolithography Basics -- 3.2.3.2 Photolithography Considerations for OTFTs -- 3.2.4 Patterning by Inkjet Printing -- 3.2.4.1 Inkjet Printing of OTFTs -- 3.2.4.2 Improved Resolution by Surface-Energy Assisted Inkjet Printing.

3.2.4.3 Printing Peripheral Circuit: Vias and Interconnects -- 3.2.5 Microcontact Printing -- 3.2.6 Other Deposition Methods -- 3.3 OTFT Fabrication Schemes -- 3.3.1 Basic One-Mask Processing Scheme for Bottom-Gate OTFT -- 3.3.2 Photolithography Scheme for Fully-Patterned and Fully-Encapsulated Bottom-Gate OTFT -- 3.3.2.1 Directly Patterned OTFTs -- 3.3.2.2 Indirectly Patterned OTFTs -- 3.3.3 Hybrid Photolithography-Inkjet Printing Scheme for Fully-Patterned Bottom-Gate OTFT -- 3.3.4 Photolithography Scheme for Top-Gate and Dual-Gate OTFTs -- 3.3.4.1 Top-Gate OTFT -- 3.3.4.2 Dual-Gate OTFT -- 3.3.4.3 Analysis -- 3.3.5 Fabrication Scheme Comparisons -- 3.4 Summary and Contributions -- References -- 4 Gate Dielectrics by Plasma Enhanced Chemical Vapor Deposition (PECVD) -- 4.1 Overview of Gate Dielectrics -- 4.1.1 Organic Dielectrics -- 4.1.2 Inorganic Dielectrics -- 4.2 Experimental Details and Characterization Methods -- 4.2.1 Deposition Conditions of PECVD Silicon Nitride (SiNx) -- 4.2.2 Thin Film Characterization Methods -- 4.2.2.1 Fourier Transform Infrared Spectroscopy (FTIR) -- 4.2.2.2 Ellipsometry -- 4.2.2.3 X-Ray Photoelectron Spectroscopy (XPS) -- 4.2.2.4 Atomic Force Microscopy (AFM) -- 4.2.2.5 Contact Angle Analysis -- 4.3 Material Characterization of PECVD SiNx Films -- 4.3.1 Bulk/Structural Characterization -- 4.3.1.1 FTIR Spectroscopy -- 4.3.1.2 Refractive Index -- 4.3.1.3 [N]/[Si] Ratio -- 4.3.2 Surface Characterization -- 4.3.2.1 Contact Angle -- 4.3.2.2 Surface Morphology and Roughness -- 4.3.2.3 Chemical Composition -- 4.3.3 Electrical Characterization -- 4.3.3.1 I-V Measurements -- 4.3.3.2 C-V Measurements -- 4.3.4 Summary -- 4.4 Electrical Characterization of OTFTs with PECVD Gate Dielectric -- 4.4.1 300ºC SiNx Gate Dielectrics -- 4.4.2 150ºC SiNx Gate Dielectrics -- 4.4.3 Stacked SiNx Gate Dielectrics.

4.4.4 200ºC SiOx Gate Dielectrics -- 4.4.5 OTFTs on Plastic Substrates -- 4.5 Summary and Contributions -- References -- 5 Dielectric Interface Engineering -- 5.1 Background -- 5.1.1 Self Assembled Monolayer (SAM) -- 5.1.2 Oxygen Plasma Treatment -- 5.1.2.1 Basics of Plasma Processing (Etching) -- 5.2 Experimental Details -- 5.3 Impact of Dielectric Surface Treatments -- 5.4.1 Electrical Characterization -- 5.4.1.1 Impact of Exposure Duration -- 5.4.1.2 Impact of Exposure Power -- 5.4.2 Interface Characterization -- 5.4.2.1 Contact Angle -- 5.4.2.2 Surface Roughness -- 5.4.2.3 Chemical Composition -- 5.4.2.4 XPS Depth Profile Analysis -- 5.4.3 Analysis and Discussion -- 5.3.1 Electrical Characterization -- 5.3.2 Interface Characterization -- 5.3.2.1 Contact Angle -- 5.3.2.2 Surface Roughness -- 5.3.2.3 Chemical Composition -- 5.3.3 Analysis -- 5.4 Impact of Oxygen Plasma Exposure Conditions -- 5.5 Summary and Contributions -- References -- 6 Contact Interface Engineering -- 6.1 Background -- 6.1.1 Charge Injection -- 6.1.2 Alkanethiol SAM on Metals -- 6.2 Experimental Details -- 6.3 Impact of Contact Surface Treatment by Thiol SAM -- 6.3.1 Electrical Characterization -- 6.3.2 Interface Characterization -- 6.3.2.1 Contact Angle -- 6.3.2.2 Surface Roughness -- 6.3.2.3 Chemical Composition -- 6.3.3 Analysis -- 6.4 Impact of Execution Sequence of Surface Treatment -- 6.4.1 Electrical Characterization -- 6.4.2 Interface Characterization -- 6.4.2.1 Contact Angle -- 6.4.2.2 Surface Roughness -- 6.4.2.3 Chemical Composition -- 6.5 Summary and Contributions -- References -- Further Reading -- 7 OTFT Circuits and Systems -- 7.1 OTFT Requirements for Circuit Applications -- 7.1.1 Speed -- 7.1.2 Leakage -- 7.1.3 Current Drive Capacity -- 7.1.4 Stability -- 7.2 Applications -- 7.2.1 Displays -- 7.2.2 RFID Tags -- 7.3 Circuit Demonstration.

7.3.1 Fabrication Schemes -- 7.3.2 Inverters -- 7.3.3 Current Mirrors -- 7.3.4 Ring Oscillators -- 7.3.5 Display Pixel Circuits -- 7.3.5.1 Conventional 2-TFT Pixel Circuit -- 7.3.5.2 Compensating 2-TFT Pixel Circuit -- 7.3.5.3 4-TFT Current Mirror Pixel Circuit -- 7.4 Summary, Contributions, and Outlook -- 7.4.1 Active-Matrix Backplane Integration -- 7.4.2 Back-End Process Integration: Bonding and Packaging -- References -- Further Reading -- 8 Outlook and Future Challenges -- 8.1 Device Performance -- 8.2 Device Manufacture -- 8.3 Device Integration -- References -- Index.