Embedded SOPC Design with Nios II Processor and VHDL Examples -- CONTENTS -- Preface -- Acknowledgments -- 1 Overview of Embedded System -- 1.1 Introduction -- 1.1.1 Definition of an embedded system -- 1.1.2 Example systems -- 1.2 System design requirements -- 1.3 Embedded SoPC systems -- 1.3.1 Basic development flow -- 1.4 Book organization -- 1.5 Bibliographic notes -- PART I BASIC DIGITAL CIRCUITS DEVELOPMENT -- 2 Gate-level Combinational Circuit -- 2.1 Overview of VHDL -- 2.2 General description -- 2.2.1 Basic lexical rules -- 2.2.2 Library and package -- 2.2.3 Entity declaration -- 2.2.4 Data type and operators -- 2.2.5 Architecture body -- 2.2.6 Code of a 2-bit comparator -- 2.3 Structural description -- 2.4 Testbench -- 2.5 Bibliographic notes -- 2.6 Suggested experiments -- 2.6.1 Code for gate-level greater-than circuit -- 2.6.2 Code for gate-level binary decoder -- 3 Overview of FPGA and EDA Software -- 3.1 FPGA -- 3.1.1 Overview of a general FPGA device -- 3.1.2 Overview of the Altera Cyclone II devices -- 3.2 Overview of the Altera DE1 and DE2 boards -- 3.3 Development flow -- 3.4 Overview of Quartus II -- 3.5 Short tutorial of Quartus II -- 3.5.1 Create the design project -- 3.5.2 Create a testbench and perform the RTL simulation -- 3.5.3 Compile the project -- 3.5.4 Perform timing analysis -- 3.5.5 Program the FPGA device -- 3.6 Short tutorial on the ModelSim HDL simulator -- 3.7 Bibliographic notes -- 3.8 Suggested experiments -- 3.8.1 Gate-level greater-than circuit -- 3.8.2 Gate-level binary decoder -- 4 RT-level Combinational Circuit -- 4.1 RT-level components -- 4.1.1 Relational operators -- 4.1.2 Arithmetic operators -- 4.1.3 Other synthesis-related VHDL constructs -- 4.1.4 Summary -- 4.2 Routing circuit with concurrent assignment statements -- 4.2.1 Conditional signal assignment statement.

4.2.2 Selected signal assignment statement -- 4.3 Modeling with a process -- 4.3.1 Process -- 4.3.2 Sequential signal assignment statement -- 4.4 Routing circuit with if and case statements -- 4.4.1 If statement -- 4.4.2 Case statement -- 4.4.3 Comparison to concurrent statements -- 4.4.4 Unintended memory -- 4.5 Constants and generics -- 4.5.1 Constants -- 4.5.2 Generics -- 4.6 Design examples -- 4.6.1 Hexadecimal digit to seven-segment LED decoder -- 4.6.2 Sign-magnitude adder -- 4.6.3 Barrel shifter -- 4.6.4 Simplified floating-point adder -- 4.7 Bibliographic notes -- 4.8 Suggested experiments -- 4.8.1 Multi-function barrel shifter -- 4.8.2 Dual-priority encoder -- 4.8.3 BCD incrementor -- 4.8.4 Floating-point greater-than circuit -- 4.8.5 Floating-point and signed integer conversion circuit -- 4.8.6 Enhanced floating-point adder -- 5 Regular Sequential Circuit -- 5.1 Introduction -- 5.1.1 D FF and register -- 5.1.2 Synchronous system -- 5.1.3 Code development -- 5.2 HDL code of the basic storage elements -- 5.2.1 D FF -- 5.2.2 Register -- 5.2.3 Register file -- 5.2.4 SRAM -- 5.3 Simple design examples -- 5.3.1 Shift register -- 5.3.2 Binary counter and variant -- 5.4 Testbench for sequential circuits -- 5.5 Timing analysis -- 5.5.1 Timing parameters -- 5.5.2 Timing considerations in Quartus II -- 5.6 Case study -- 5.6.1 Stopwatch -- 5.6.2 FIFO buffer -- 5.7 Cyclone II device embedded memory module -- 5.7.1 Overview of memory options of DE1 board -- 5.7.2 Overview of embedded M4K module -- 5.7.3 Methods to incorporate embedded memory module -- 5.7.4 HDL module to infer synchronous single-port RAM -- 5.7.5 HDL module to infer synchronous simple dual-port RAM -- 5.7.6 HDL module to infer synchronous true dual-port RAM -- 5.7.7 HDL module to infer synchronous ROM -- 5.7.8 FIFO buffer revisited -- 5.8 Bibliographic notes -- 5.9 Suggested experiments.

5.9.1 Programmable square wave generator -- 5.9.2 Pulse width modulation circuit -- 5.9.3 Rotating square circuit -- 5.9.4 Heartbeat circuit -- 5.9.5 Rotating LED banner circuit -- 5.9.6 Enhanced stopwatch -- 5.9.7 FIFO with data width conversion -- 5.9.8 Stack -- 5.9.9 ROM-based sign-magnitude adder -- 5.9.10 ROM-based temperature conversion -- 6 FSM -- 6.1 Introduction -- 6.1.1 Mealy and Moore outputs -- 6.1.2 FSM representation -- 6.2 FSM code development -- 6.3 Design examples -- 6.3.1 Rising-edge detector -- 6.3.2 Debouncing circuit -- 6.3.3 Testing circuit -- 6.4 Bibliographic notes -- 6.5 Suggested experiments -- 6.5.1 Dual-edge detector -- 6.5.2 Alternative debouncing circuit -- 6.5.3 Parking lot occupancy counter -- 7 FSMD -- 7.1 Introduction -- 7.1.1 Single RT operation -- 7.1.2 ASMD chart -- 7.1.3 Decision box with a register -- 7.2 Code development of an FSMD -- 7.2.1 Debouncing circuit based on RT methodology -- 7.2.2 Code with explicit data path components -- 7.2.3 Code with implicit data path components -- 7.2.4 Comparison -- 7.3 Design examples -- 7.3.1 Fibonacci number circuit -- 7.3.2 Division circuit -- 7.3.3 Binary-to-BCD conversion circuit -- 7.3.4 Period counter -- 7.3.5 Accurate low-frequency counter -- 7.4 Bibliographic notes -- 7.5 Suggested experiments -- 7.5.1 Alternative debouncing circuit -- 7.5.2 BCD-to-binary conversion circuit -- 7.5.3 Fibonacci circuit with BCD I/O: design approach 1 -- 7.5.4 Fibonacci circuit with BCD I/O: design approach 2 -- 7.5.5 Auto-scaled low-frequency counter -- 7.5.6 Reaction timer -- 7.5.7 Babbage difference engine emulation circuit -- PART II BASIC NIOS II SOFTWARE DEVELOPMENT -- 8 Nios II Processor Overview -- 8.1 Introduction -- 8.2 Register file and ALU -- 8.2.1 Register file -- 8.2.2 ALU -- 8.3 Memory and I/O organization -- 8.3.1 Nios II memory interface.

8.3.2 Overview of memory hierarchy -- 8.3.3 Virtual memory -- 8.3.4 Memory protection -- 8.3.5 Cache memory -- 8.3.6 Tightly coupled memory -- 8.3.7 I/O organization -- 8.3.8 Interconnect structure -- 8.4 Exception and interrupt handler -- 8.5 JTAG debug module -- 8.6 Bibliographic notes -- 8.7 Suggested projects -- 8.7.1 Comparison of Nios II and MIPS -- 9 Nios II System Derivation and Low-Level Access -- 9.1 Development flow revisited -- 9.1.1 Hardware development -- 9.1.2 Software development -- 9.1.3 Flashing-LED system -- 9.2 Nios II hardware generation tutorial -- 9.2.1 Create a hardware project in Quartus II -- 9.2.2 Create a Nios II system and generate HDL codes -- 9.2.3 Create a top-level HDL file that instantiates the Nios II system -- 9.2.4 Compiling and programming -- 9.3 Nios II SBT GUI tutorial -- 9.3.1 Create BSP library -- 9.3.2 Configure the BSP using BSP Editor -- 9.3.3 Create user application directory and add application files -- 9.3.4 Build and run software -- 9.3.5 Check code size -- 9.4 System id core for hardware-software consistency -- 9.5 Direct low-level I/O access -- 9.5.1 Review of C pointer -- 9.5.2 C pointer for I/O register -- 9.6 Robust low-level I/O access -- 9.6.1 system.h -- 9.6.2 alt_types.h -- 9.6.3 io.h -- 9.7 Some C techniques for low-level I/O operations -- 9.7.1 Bit manipulation -- 9.7.2 Packing and unpacking -- 9.8 Software development -- 9.8.1 Basic embedded program architecture -- 9.8.2 Main program and task routines -- 9.9 Bibliographic notes -- 9.10 Suggested experiments -- 9.10.1 Chasing LED circuit -- 9.10.2 Collision LED circuit -- 9.10.3 Pulse width modulation circuit -- 9.10.4 Rotating square circuit -- 9.10.5 Heartbeat circuit -- 9.11 Complete program listing -- 10 Predesigned Nios II I/O Peripherals -- 10.1 Overviews -- 10.2 PIO core -- 10.2.1 Configuration -- 10.2.2 Register map.

10.2.3 Visible register -- 10.3 JTAG UART core -- 10.3.1 Configuration -- 10.3.2 Register map -- 10.4 Internal timer core -- 10.4.1 Configuration -- 10.4.2 Register map -- 10.5 Enhanced flashing-LED Nios II system -- 10.5.1 SOPC design -- 10.5.2 Top-level HDL file -- 10.6 Software development of enhanced flashing-LED system -- 10.6.1 Introduction to device driver -- 10.6.2 Program structure of the enhanced flashing-LED system -- 10.6.3 Main program -- 10.6.4 Function naming convention -- 10.7 Device driver routines -- 10.7.1 Driver for PIO peripherals -- 10.7.2 JTAG UART -- 10.7.3 Timer -- 10.8 Task routines -- 10.8.1 The flashsys-init_v1() function -- 10.8.2 The sw_get_command_v1() function -- 10.8.3 The jtaguart_disp_msg.v1() function -- 10.8.4 The sseg_disp_msg-v1() function -- 10.8.5 The led_flash_v1() function -- 10.9 Software construction and testing -- 10.10 Bibliographic notes -- 10.11 Suggested experiments -- 10.11.1 "Uptime" feature in flashing-LED system -- 10.11.2 Counting with different timer mode -- 10.11.3 JTAG UART input -- 10.11.4 Enhanced collision LED circuit -- 10.11.5 Rotating LED banner circuit -- 10.11.6 Enhanced stopwatch -- 10.11.7 Parking lot occupancy counter -- 10.11.8 Reaction timer with pushbutton switch control -- 10.11.9 Reaction timer with keyboard control -- 10.11.10 Communication with serial port -- 10.12 Complete program listing -- 11 Predesigned Nios II I/O Drivers and HAL API -- 11.1 Overview of HAL -- 11.1.1 Desktop-like and barebone embedded systems -- 11.1.2 HAL paradigm -- 11.1.3 Device classes -- 11.1.4 HAL-compliant device drivers -- 11.1.5 The _regs.h file -- 11.1.6 HAL-based initialization sequence -- 11.2 BSP -- 11.2.1 Overview -- 11.2.2 BSP file structure -- 11.2.3 BSP configuration -- 11.3 HAL-based flashing-LED program -- 11.3.1 Functions using generic I/O devices.

11.3.2 Functions using non-generic I/O devices.