Embedded SoPC Design With Nios II Processor And Verilog Examples -- Contents -- Preface -- Acknowledgments -- 1 Overview of Embedded System -- 1.1 Introduction -- 1.1.1 Definition of an embedded system -- 1.1.2 Example systems -- 1.2 System design requirements -- 1.3 Embedded SoPC systems -- 1.3.1 Basic development flow -- 1.4 Book organization -- 1.5 Bibliographic notes -- PART I BASIC DIGITAL CIRCUITS DEVELOPMENT -- 2 Gate-level Combinational Circuit -- 2.1 Introduction -- 2.2 General description -- 2.3 Basic lexical elements and data types -- 2.3.1 Lexical elements -- 2.4 Data types -- 2.4.1 Four-value system -- 2.4.2 Data type groups -- 2.4.3 Number representation -- 2.4.4 Operators -- 2.5 Program skeleton -- 2.5.1 Port declaration -- 2.5.2 Program body -- 2.5.3 Signal declaration -- 2.5.4 Another example -- 2.6 Structural description -- 2.7 Testbench -- 2.8 Bibliographic notes -- 2.9 Suggested experiments -- 2.9.1 Code for gate-level greater-than circuit -- 2.9.2 Code for gate-level binary decoder -- 3 Overview of FPGA and EDA Software -- 3.1 FPGA -- 3.1.1 Overview of a general FPGA device -- 3.1.2 Overview of the Altera Cyclone II devices -- 3.2 Overview of the Altera DEI and DE2 boards -- 3.3 Development flow -- 3.4 Overview of Quartus II -- 3.5 Short tutorial of Quartus II -- 3.5.1 Create the design project -- 3.5.2 Create a testbench and perform the RTL simulation -- 3.5.3 Compile the project -- 3.5.4 Perform timing analysis -- 3.5.5 Program the FPGA device -- 3.6 Short tutorial on the ModelSim HDL simulator -- 3.7 Bibliographic notes -- 3.8 Suggested experiments -- 3.8.1 Gate-level greater-than circuit -- 3.8.2 Gate-level binary decoder -- 4 RT-level Combinational Circuit -- 4.1 Operators -- 4.1.1 Arithmetic operators -- 4.1.2 Shift operators -- 4.1.3 Relational and equality operators -- 4.1.4 Bitwise, reduction, and logical operators.

4.1.5 Concatenation and replication operators -- 4.1.6 Conditional operators -- 4.1.7 Operator precedence -- 4.1.8 Expression bit-length adjustment -- 4.1.9 Synthesis of z and x values -- 4.2 Always block for a combinational circuit -- 4.2.1 Basic syntax and behavior -- 4.2.2 Procedural assignment -- 4.2.3 Variable data types -- 4.2.4 Simple examples -- 4.3 If statement -- 4.3.1 Syntax -- 4.3.2 Examples -- 4.4 Case statement -- 4.4.1 Syntax -- 4.4.2 Examples -- 4.4.3 The casez and casex statements -- 4.4.4 Full case and parallel case -- 4.5 Routing structure of conditional control constructs -- 4.5.1 Priority routing network -- 4.5.2 Multiplexing network -- 4.6 General coding guidelines for an always block -- 4.6.1 Common errors in combinational circuit codes -- 4.6.2 Guidelines -- 4.7 Parameter and constant -- 4.7.1 Constant -- 4.7.2 Parameter -- 4.7.3 Use of parameters in Verilog-1995 -- 4.8 Design examples -- 4.8.1 Hexadecimal digit to seven-segment LED decoder -- 4.8.2 Sign-magnitude adder -- 4.8.3 Barrel shifter -- 4.8.4 Simplified floating-point adder -- 4.9 Bibliographic notes -- 4.10 Suggested experiments -- 4.10.1 Multifunction barrel shifter -- 4.10.2 Dual-priority encoder -- 4.10.3 BCD incrementor -- 4.10.4 Floating-point greater-than circuit -- 4.10.5 Floating-point and signed integer conversion circuit -- 4.10.6 Enhanced floating-point adder -- 5 Regular Sequential Circuit -- 5.1 Introduction -- 5.1.1 D FF and register -- 5.1.2 Synchronous system -- 5.1.3 Code development -- 5.2 HDL code of the FF and register -- 5.2.1 D FF -- 5.2.2 Register -- 5.2.3 Register file -- 5.2.4 SRAM -- 5.3 Simple design examples -- 5.3.1 Shift register -- 5.3.2 Binary counter and variant -- 5.4 Testbench for sequential circuits -- 5.5 Timing analysis -- 5.5.1 Timing parameters -- 5.5.2 Timing considerations in Quartus II -- 5.6 Case study -- 5.6.1 Stopwatch.

5.6.2 FIFO buffer -- 5.7 Cyclone II device embedded memory module -- 5.7.1 Overview of memory options of DE1 board -- 5.7.2 Overview of embedded M4K module -- 5.7.3 Methods to incorporate embedded memory module -- 5.7.4 HDL module to infer synchronous single-port RAM -- 5.7.5 HDL module to infer synchronous simple dual-port RAM -- 5.7.6 HDL module to infer synchronous true dual-port RAM -- 5.7.7 HDL module to infer synchronous ROM -- 5.7.8 HDL module to specify RAM initial values -- 5.7.9 FIFO buffer revisited -- 5.8 Bibliographic notes -- 5.9 Suggested experiments -- 5.9.1 Programmable square-wave generator -- 5.9.2 Pulse width modulation circuit -- 5.9.3 Rotating square circuit -- 5.9.4 Heartbeat circuit -- 5.9.5 Rotating LED banner circuit -- 5.9.6 Enhanced stopwatch -- 5.9.7 FIFO with data width conversion -- 5.9.8 Stack -- 5.9.9 ROM-based sign-magnitude adder -- 5.9.10 ROM-based temperature conversion -- 6 FSM -- 6.1 Introduction -- 6.1.1 Mealy and Moore outputs -- 6.1.2 FSM representation -- 6.2 FSM code development -- 6.3 Design examples -- 6.3.1 Rising-edge detector -- 6.3.2 Debouncing circuit -- 6.3.3 Testing circuit -- 6.4 Bibliographic notes -- 6.5 Suggested experiments -- 6.5.1 Dual-edge detector -- 6.5.2 Alternative debouncing circuit -- 6.5.3 Parking lot occupancy counter -- 7 FSMD -- 7.1 Introduction -- 7.1.1 Single RT operation -- 7.1.2 ASMD chart -- 7.1.3 Decision box with a register -- 7.2 Code development of an FSMD -- 7.2.1 Debouncing circuit based on RT methodology -- 7.2.2 Code with explicit data path components -- 7.2.3 Code with implicit data path components -- 7.2.4 Comparison -- 7.3 Design examples -- 7.3.1 Fibonacci number circuit -- 7.3.2 Division circuit -- 7.3.3 Binary-to-BCD conversion circuit -- 7.3.4 Period counter -- 7.3.5 Accurate low-frequency counter -- 7.4 Bibliographic notes -- 7.5 Suggested experiments.

7.5.1 Alternative debouncing circuit -- 7.5.2 BCD-to-binary conversion circuit -- 7.5.3 Fibonacci circuit with BCD I/O: design approach 1 -- 7.5.4 Fibonacci circuit with BCD I/O: design approach 2 -- 7.5.5 Auto-scaled low-frequency counter -- 7.5.6 Reaction timer -- 7.5.7 Babbage difference engine emulation circuit -- 8 Selected Topics of Verilog -- 8.1 Blocking versus nonblocking assignment -- 8.1.1 Overview -- 8.1.2 Combinational circuit -- 8.1.3 Memory element -- 8.1.4 Sequential circuit with mixed blocking and nonblocking assignments -- 8.2 Alternative coding style for sequential circuit -- 8.2.1 Binary counter -- 8.2.2 FSM -- 8.2.3 FSMD -- 8.2.4 Summary -- 8.3 Use of the signed data type -- 8.3.1 Overview -- 8.3.2 Signed number in Verilog-1995 -- 8.3.3 Signed number in Verilog-2001 -- 8.4 Use of function in synthesis -- 8.4.1 Overview -- 8.4.2 Examples -- 8.5 Additional constructs for testbench development -- 8.5.1 Always block and initial block -- 8.5.2 Procedural statements -- 8.5.3 Timing control -- 8.5.4 Delay control -- 8.5.5 Event control -- 8.5.6 Wait statement -- 8.5.7 Timescale directive -- 8.5.8 System functions and tasks -- 8.5.9 User-defined functions and tasks -- 8.5.10 Example of a comprehensive testbench -- 8.6 Bibliographic notes -- 8.7 Suggested experiments -- 8.7.1 Shift register with blocking and nonblocking assignments -- 8.7.2 Alternative coding style for BCD counter -- 8.7.3 Alternative coding style for FIFO buffer -- 8.7.4 Alternative coding style for Fibonacci circuit -- 8.7.5 Dual-mode comparator -- 8.7.6 Enhanced binary counter monitor -- 8.7.7 Testbench for FIFO buffer -- PART II BASIC NIOS II SOFTWARE DEVELOPMENT -- 9 Nios II Processor Overview -- 9.1 Introduction -- 9.2 Register file and ALU -- 9.2.1 Register file -- 9.2.2 ALU -- 9.3 Memory and I/O organization -- 9.3.1 Nios II memory interface.

9.3.2 Overview of memory hierarchy -- 9.3.3 Virtual memory -- 9.3.4 Memory protection -- 9.3.5 Cache memory -- 9.3.6 Tightly coupled memory -- 9.3.7 I/O organization -- 9.3.8 Interconnect structure -- 9.4 Exception and interrupt handler -- 9.5 JTAG debug module -- 9.6 Bibliographic notes -- 9.7 Suggested projects -- 9.7.1 Comparison of Nios II and MIPS -- 10 Nios II System Derivation and Low-Level Access -- 10.1 Development flow revisited -- 10.1.1 Hardware development -- 10.1.2 Software development -- 10.1.3 Flashing-LED system -- 10.2 Nios II hardware generation tutorial -- 10.2.1 Create a hardware project in Quartus II -- 10.2.2 Create a Nios II system and generate HDL codes -- 10.2.3 Create a top-level HDL file that instantiates the Nios II system -- 10.2.4 Compiling and programming -- 10.3 Nios II SBT GUI tutorial -- 10.3.1 Create BSP library -- 10.3.2 Configure the BSP using BSP Editor -- 10.3.3 Create user application directory and add application files -- 10.3.4 Build and run software -- 10.3.5 Check code size -- 10.4 System id core for hardware-software consistency -- 10.5 Direct low-level I/O access -- 10.5.1 Review of C pointer -- 10.5.2 C pointer for I/O register -- 10.6 Robust low-level I/O access -- 10.6.1 system.h -- 10.6.2 alt_types.h -- 10.6.3 io.h -- 10.7 Some C techniques for low-level I/O operations -- 10.7.1 Bit manipulation -- 10.7.2 Packing and unpacking -- 10.8 Software development -- 10.8.1 Basic embedded program architecture -- 10.8.2 Main program and task routines -- 10.9 Bibliographic notes -- 10.10 Suggested experiments -- 10.10.1 Chasing LED circuit -- 10.10.2 Collision LED circuit -- 10.10.3 Pulse width modulation circuit -- 10.10.4 Rotating square circuit -- 10.10.5 Heartbeat circuit -- 10.11 Complete program listing -- 11 Predesigned Nios II I/O Peripherals -- 11.1 Overviews -- 11.2 PIO core -- 11.2.1 Configuration.

11.2.2 Register map.