Engineering the CMOS Library : Enhancing Digital Design Kits for Competitive Silicon.
Title:
Engineering the CMOS Library : Enhancing Digital Design Kits for Competitive Silicon.
Author:
Doman, David.
ISBN:
9781118273111
Personal Author:
Edition:
1st ed.
Physical Description:
1 online resource (343 pages)
Contents:
Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon -- Contents -- Preface -- Acknowledgments -- 1: Introduction -- 1.1: Adding Project-Specific Functions, Drive Strengths, Views, and Corners -- 1.2: What Is a DDK? -- 2: Stdcell Libraries -- 2.1: Lesson from the Real World: Manager's Perspective and Engineer's Perspective -- 2.2: What Is a Stdcell? -- 2.2.1: Combinational Functions -- 2.2.2: Sequential Functions -- 2.2.3: Clock Functions -- 2.3: Extended Library Offerings -- 2.3.1: Low-Power Support -- 2.4: Boutique Library Offerings -- 2.5: Concepts for Further Study -- 3: IO Libraries -- 3.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective -- 3.2: Extension Capable Architectures versus Function Complete Architectures -- 3.3: Electrostatic Discharge Considerations -- 3.3.1: Footprints -- 3.3.2: Custom Design Versus Standard IO Design Comparison -- 3.3.3: The Need for Maintaining Multiple IO Footprint Regions on an IC -- 3.3.4: Circuit Under Pad -- 3.4: Concepts for Further Study -- 4: Memory Compilers -- 4.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective -- 4.2: Single Ports, Dual Ports, and ROM: The Compiler -- 4.3: Nonvolatile Memories: The Block -- 4.4: Special-Purpose Memories: The Custom -- 4.5: Concepts for Further Study -- 5: Other Functions -- 5.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective -- 5.2: Phase-Locked Loops, Power-On Resets, and Other Small-Scale Integration Analogs -- 5.3: Low-Power Support Structures -- 5.4: Stitching Structures -- 5.4.1: Core-Fill Cells -- 5.4.2: IO-Fill Cells -- 5.4.3: DECAP Cells -- 5.4.4: CMP-Fill Cells -- 5.4.5: Spare Logic Cells -- 5.4.6: Probe-Point Cells -- 5.4.7: Antenna Diodes -- 5.4.8: Test-Debug Diodes -- 5.4.9: Others.
5.5: Hard, Firm, and Soft Boxes -- 5.6: Concepts for Further Study -- 6: Physical Views -- 6.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective -- 6.2: Picking an Architecture -- 6.3: Measuring Density -- 6.4: The Need and the Way to Work with Fabrication Houses -- 6.5: Concepts for Further Study -- 7: SPICE -- 7.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective -- 7.2: Why a Tool More Than 40 Years Old Is Still Useful -- 7.3: Accuracy, Reality, and Why SPICE Results Must be Viewed with a Wary Eye -- 7.4: Sufficient Parasitics -- 7.5: Concepts for Further Study -- 8: Timing Views -- 8.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective -- 8.2: Performance Limits and Measurement -- 8.3: Default Versus Conditional Arcs -- 8.4: Break-Point Optimization -- 8.5: A Word on Setup and Hold -- 8.6: Failure Mechanisms and Roll-Off -- 8.7: Supporting Efficient Synthesis -- 8.7.1: SPICE, Monotonic Arrays, and Favorite Stdcells -- 8.7.2: SPICE, Positive Arrays, and Useful Skew -- 8.8: Supporting Efficient Timing Closure -- 8.9: Design Corner Specific Timing Views -- 8.10: Nonlinear Timing Views are so "Old Hat" . . . -- 8.11: Concepts for Further Study -- 9: Power Views -- 9.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective -- 9.2: Timing Arcs Versus Power Arcs -- 9.3: Static Power -- 9.4: Real Versus Measured Dynamic Power -- 9.5: Should Power Be Built as a Monotonic Array? -- 9.6: Best-Case and Worst-case Power Views Versus Best-Case and Worst-Case Timing Views -- 9.7: Efficiently Measuring Power -- 9.8: Concepts for Further Study -- 10: Noise Views -- 10.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective -- 10.2: Noise Arcs Versus Timing and Power Arcs -- 10.3: The Easy Part.
10.4: The Not-So-Easy Part -- 10.5: Concepts for Further Study -- 11: Logical Views -- 11.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective -- 11.2: Consistency Across Simulators -- 11.2.1: Efficient Testing -- 11.3: Consistency with Timing, Power & Noise Views -- 11.4: Concepts for Further Study -- 12: Test Views -- 12.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective -- 12.2: Supporting Reachability -- 12.3: Supporting Observability -- 12.4: Concepts for Further Study -- 13: Consistency -- 13.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective -- 13.2: Validating Views across a Library -- 13.3: Validating Stdcells Across a Technology Node -- 13.4: Validating Libraries Across Multiple Technology Nodes -- 13.5: Concepts for Further Study -- 14: Design for Manufacturability -- 14.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective -- 14.2: What is DFM? -- 14.2.1: Design for Manufacturability or Design for Mediocrity? -- 14.2.2: Design for Methodology and Design for Mobility (Between Fabrication Houses)? -- 14.2.3: Design for Models and Design for Measurement -- 14.2.4: Design for Management and Design for Metrics -- 14.2.5: Design for Market -- 14.2.6: Design for Money -- 14.3: Concepts for Further Study -- 15: Validation -- 15.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective -- 15.2: Quality Levels -- 15.2.1: Tin: Engineering Work in Progress -- 15.2.2: Silver: Expert Use Only -- 15.2.3: Gold: Ready for General Use -- 15.2.4: Platinum: Long-Standing and Stable -- 15.3: Concepts for Further Study -- 16: Playing with the Physical Design Kit: Usually "At Your Own Risk" -- 16.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective.
16.2: Manipulating Models -- 16.3: Added Unsupported Devices -- 16.4: Concepts for Further Study -- 17: Tagging and Revisioning -- 17.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective -- 17.2: Tagging and Time Stamps -- 17.2.1: ASCII -- 17.2.2: Binary -- 17.3: Metadata, Directory Structures, and Pointers -- 17.4: Concepts for Further Study -- 18: Releasing and Supporting -- 18.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective -- 18.2: When Is Test Silicon Needed for Verification? -- 18.3: Sending the Baby Out the Door -- 18.3.1: Validation Reports -- 18.3.2: Verification Reports -- 18.4: Multiple Quality Levels on the Same Design -- 18.5: Supporting "Bug Fixes" -- 18.6: Concepts for Further Study -- 19: Other Topics -- 19.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective -- 19.2: Supporting High-Speed Design -- 19.3: Supporting Low-Power Design -- 19.4: Supporting Third-Party Libraries -- 19.5: Supporting Black Box Third-Party IP (Intellectual Property) Design -- 19.6: Supporting Multiple Library Design -- 19.7: Concepts for Further Study -- 20: Communications -- 20.1: Manager's Perspective -- 20.2: Customer's Perspective -- 20.3: Vendor's Perspective -- 20.4: Engineer's Perspective -- 20.5: Concepts for Further Study -- 20.6: Conclusions -- Appendix I: Minimum Library Synthesis Versus Full-Library Synthesis of A Four-Bit Flash Adder -- Appendix II: Pertinent CMOS BSIM SPICE Parameters with Units and Default Levels -- Appendix III: Definition of Terms -- Appendix IV: One Possible Means of Formalized Monthly Reporting -- Index.
Abstract:
Shows readers how to gain the competitive edge in the integrated circuit marketplace This book offers a wholly unique perspective on the digital design kit. It points to hidden value in the safety margins of standard-cell libraries and shows design engineers and managers how to use this knowledge to beat the competition. Engineering the CMOS Library reveals step by step how the generic, foundry-provided standard-cell library is built, and how to extract value from existing std-cells and EDA tools in order to produce tighter-margined, smaller, faster, less power-hungry, and more yield-producing integrated circuits. It explores all aspects of the digital design kit, including the different views of CMOS std-cell libraries along with coverage of IO libraries, memory compilers, and small analog blocks. Readers will learn: How to work with overdesigned std-cell libraries to improve profitability while maintaining safety How functions usually found in std-cell libraries cover the design environment, and how to add any missing functions How to harness the characterization technique used by vendors to add characterization without having to get it from the vendor How to use verification and validation techniques to ensure proper descriptive views and even fix inconsistencies in vendor release views How to correct for possible conflicts arising from multiple versions and different vendor sources in any given integrated circuit design Complete with real-world case studies, examples, and suggestions for further research, Engineering the CMOS Library will help readers become more astute designers.
Local Note:
Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2017. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries.
Genre:
Electronic Access:
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