Radio Frequency Integrated Circuit Design Second Edition -- Contents -- Foreword to the First Edition -- Preface -- Acknowledgments -- Chapter 1 Introduction to Communications Circuits -- 1.1 Introduction -- 1.2 Lower Frequency Analog Design and Microwave Design Versus Radio-Frequency Integrated Circuit Design -- 1.2.1 Impedance Levels for Microwave and Low-Frequency Analog Design -- 1.2.2 Units for Microwave and Low-Frequency Analog Design -- 1.3 Radio-Frequency Integrated Circuits Used in a Communications Transceiver -- 1.4 Overview -- References -- Chapter 2 Issues in RFIC Design: Noise, Linearity,and Signals -- 2.1 Introduction -- 2.2 Noise -- 2.2.1 Thermal Noise -- 2.2.2 Available Noise Power -- 2.2.3 Available Power from Antenna -- 2.2.4 The Concept of Noise Figure -- 2.2.5 The Noise Figure of an Amplifier Circuit -- 2.2.6 Phase Noise -- 2.3 Linearity and Distortion in RF Circuits -- 2.3.1 Power Series Expansion -- 2.3.2 Third-Order Intercept Point -- 2.3.3 Second-Order Intercept Point -- 2.3.4 The 1-dB Compression Point -- 2.3.5 Relationships Between 1-dB Compression and IP3 Points -- 2.3.6 Broadband Measures of Linearity -- 2.4 Modulated Signals -- 2.4.1 Phase Modulation -- 2.4.2 Frequency Modulation -- 2.4.3 Minimum Shift Keying (MSK) -- 2.4.4 Quadrature Amplitude Modulation (QAM) -- 2.4.5 Orthogonal Frequency Division Multiplexing (OFDM) -- References -- Chapter 3 System Level Architecture and Design Considerations -- 3.1 Transmitter and Receiver Architectures and Some Design Considerations -- 3.1.2 Direct Conversion Transceivers -- 3.1.3 Low IF Transceiver and Other Alternative Transceiver Architectures -- 3.2 System Level Considerations -- 3.2.1 The Noise Figure of Components in Series -- 3.2.2 The Linearity of Components in Series -- 3.2.3 Dynamic Range -- 3.2.4 Image Signals and Image Reject Filtering.

3.2.5 Blockers and Blocker Filtering -- 3.2.6 The Effect of Phase Noise on SNR in a Receiver -- 3.2.7 DC Offset -- 3.2.8 Second-Order Nonlinearity Issues -- 3.2.9 Receiver Automatic Gain Control Issues -- 3.2.10 EVM in Transmitters Including Phase Noise, Linearity, IQ Mismatch,EVM with OFDM Waveforms, and Nonlinearity -- 3.2.11 ADC and DAC Specifications -- 3.3 Antennas and the Link Between a Transmitter and a Receiver -- References -- Chapter 4 A Brief Review of Technology -- 4.1 Introduction -- 4.2 Bipolar Transistor Description -- 4.3 b Current Dependence -- 4.4 Small-Signal Model -- 4.5 Small-Signal Parameters -- 4.6 High-Frequency Effects -- 4.6.1 fT as a Function of Current -- 4.7 Noise in Bipolar Transistors -- 4.7.1 Thermal Noise in Transistor Components -- 4.7.2 Shot Noise -- 4.7.3 1/f Noise -- 4.8 Base Shot Noise Discussion -- 4.9 Noise Sources in the Transistor Model -- 4.10 Bipolar Transistor Design Considerations -- 4.11 CMOS Transistors -- 4.11.1 NMOS Transistor Operation -- 4.11.2 PMOS Transistor Operation -- 4.11.3 CMOS Small-Signal Model -- 4.11.4 fT and fmax for CMOS Transistors -- 4.12 Practical Considerations in Transistor Layout -- 4.12.1 Typical Transistors -- 4.12.2 Symmetry -- 4.12.3 Matching -- 4.12.4 ESD Protection and Antenna Rules -- References -- Chapter 5 Impedance Matching -- 5.1 Introduction -- 5.2 Review of the Smith Chart -- 5.3 Impedance Matching -- 5.4 Conversions Between Series and Parallel Resistor-Inductorand Resistor-Capacitor Circuits -- 5.5 Tapped Capacitors and Inductors -- 5.6 The Concept of Mutual Inductance -- 5.7 Matching Using Transformers -- 5.8 Tuning a Transformer -- 5.9 The Bandwidth of an Impedance Transformation Network -- 5.10 Quality Factor of an LC Resonator -- 5.11 Broadband Impedance Matching -- 5.12 Transmission Lines -- 5.13 S, Y, and Z Parameters -- References.

Chapter 6 The Use and Design of Passive Circuit Elements in IC Technologies -- 6.1 Introduction -- 6.2 The Technology Back End and Metalization in IC Technologies -- 6.3 Sheet Resistance and the Skin Effect -- 6.4 Parasitic Capacitance -- 6.5 Parasitic Inductance -- 6.6 Current Handling in Metal Lines -- 6.7 Poly Resistors and Diffusion Resistors -- 6.8 Metal-Insulator-Metal Capacitors and Stacked Metal Capacitors -- 6.9 Applications of On-Chip Spiral Inductors and Transformers -- 6.10 Design of Inductors and Transformers -- 6.11 Some Basic Lumped Models for Inductors -- 6.12 Calculating the Inductance of Spirals -- 6.13 Self-Resonance of Inductors -- 6.14 The Quality Factor of an Inductor -- 6.15 Characterization of an Inductor -- 6.16 Some Notes about the Proper Use of Inductors -- 6.17 Layout of Spiral Inductors -- 6.18 Isolating the Inductor -- 6.19 The Use of Slotted Ground Shields and Inductors -- 6.20 Basic Transformer Layouts in IC Technologies -- 6.21 Multilevel Inductors -- 6.22 Characterizing Transformers for Use in ICs -- 6.23 On-Chip Transmission Lines -- 6.23.1 Effect of Transmission Line -- 6.23.2 Transmission Line Examples -- 6.24 High-Frequency Measurement of On-Chip Passives and Some Common De-Embedding Techniques -- 6.25 Packaging -- References -- Chapter 7 LNA Design -- 7.1 Introduction and Basic Amplifiers -- 7.1.1 Common-Emitter/Source Amplifier (Driver) -- 7.1.2 Simplified Expressions for Widely Separated Poles -- 7.1.3 The Common-Base/Gate Amplifier (Cascode) -- 7.1.4 The Common-Collector/Drain Amplifier (Emitter/Source Follower) -- 7.2 Amplifiers with Feedback -- 7.2.1 Common-Emitter/Source with Series Feedback (Emitter/SourceDegeneration) -- 7.2.2 The Common-Emitter/Source with Shunt Feedback -- 7.3 Noise in Amplifiers -- 7.3.1 Input Referred Noise Model of the Bipolar Transistor.

7.3.2 Noise Figure of the Common-Emitter Amplifier -- 7.3.3 Noise Model of the CMOS Transistor -- 7.3.4 Input Matching of LNAs for Low Noise -- 7.3.5 Relationship Between Noise Figure and Bias Current -- 7.3.6 Effect of the Cascode on Noise Figure -- 7.3.7 Noise in the Common-Collector/Drain Amplifier -- 7.4 Linearity in Amplifiers -- 7.4.1 Exponential Nonlinearity in the Bipolar Transistor -- 7.4.2 Nonlinearity in the CMOS Transistor -- 7.4.3 Nonlinearity in the Output Impedance of the Bipolar Transistor -- 7.4.4 High-Frequency Nonlinearity in the Bipolar Transistor -- 7.4.5 Linearity in Common-Collector/Drain Configuration -- 7.5 Stability -- 7.6 Differential Amplifiers -- 7.6.1 Bipolar Differential Pair -- 7.6.2 Linearity in Bipolar Differential Pairs -- 7.6.3 CMOS Differential Pair -- 7.6.4 Linearity of the CMOS Differential Pair -- 7.7 Low Voltage Topologies for LNAs and the Use of On-Chip Transformers -- 7.8 DC Bias Networks -- 7.8.1 Temperature Effects -- 7.8.2 Temperature Independent Reference Generators -- 7.8.3 Constant GM Biasing for CMOS -- 7.9 Broadband LNA Design Example -- 7.10 Distributed Amplifiers -- 7.10.1 Transmission Lines -- 7.10.2 Steps in Designing the Distributed Amplifier -- References -- Selected Bibliography -- Chapter 8 Mixers -- 8.1 Introduction -- 8.2 Mixing with Nonlinearity -- 8.3 Basic Mixer Operation -- 8.4 Transconductance-Controlled Mixer -- 8.5 Double-Balanced Mixer -- 8.6 Mixer with Switching of Upper Quad -- 8.6.1 Why LO Switching? -- 8.6.2 Picking the LO Level -- 8.6.3 Analysis of Switching Modulator -- 8.7 Mixer Noise -- 8.7.1 Summary of Bipolar Mixer Noise Components -- 8.7.2 Summary of CMOS Mixer Noise Components -- 8.8 Linearity -- 8.8.1 Desired Nonlinearity -- 8.8.2 Undesired Nonlinearity -- 8.9 Improving Isolation -- 8.10 General Design Comments -- 8.10.1 Sizing Transistors -- 8.10.2 Increasing Gain.

8.10.3 Improvement of IP3 -- 8.10.4 Improving Noise Figure -- 8.10.5 Effect of Bond Pads and the Package -- 8.10.6 Matching, Bias Resistors, Gain -- 8.11 Image-Reject and Single-Sideband Mixer -- 8.11.1 Alternative Single-Sideband Mixers -- 8.11.2 Generating 90° Phase Shift -- 8.11.3 Image Rejection with Amplitude and Phase Mismatch -- 8.12 Alternative Mixer Designs -- 8.12.1 The Moore Mixer -- 8.12.2 Mixers with Transformer Input -- 8.12.3 Mixer with Simultaneous Noise and Power Match -- 8.12.4 Mixers with Coupling Capacitors -- 8.12.5 CMOS Mixer with Current Reuse -- 8.12.6 Integrated Passive Mixer -- 8.12.7 Subsampling Mixer -- References -- Selected Bibliography -- Chapter 9 Voltage Controlled Oscillators -- 9.1 Introduction -- 9.2 The LC Resonator -- 9.3 Adding Negative Resistance Through Feedback to the Resonator -- 9.4 Popular Implementations of Feedback to the Resonator -- 9.5 Configuration of the Amplifier (Colpitts or -Gm) -- 9.6 Analysis of an Oscillator as a Feedback System -- 9.6.1 Oscillator Closed-Loop Analysis -- 9.6.2 Capacitor Ratios with Colpitts Oscillators -- 9.6.3 Oscillator Open-Loop Analysis -- 9.6.4 Simplified Loop Gain Estimates -- 9.7 Negative Resistance Generated by the Amplifier -- 9.7.1 Negative Resistance of the Colpitts Oscillator -- 9.7.2 Negative Resistance for Series and Parallel Circuits -- 9.7.3 Negative Resistance Analysis of -Gm Oscillator -- 9.8 Comments on Oscillator Analysis -- 9.9 Basic Differential Oscillator Topologies -- 9.10 A Modified Common-Collector Colpitts Oscillator with Buffering -- 9.11 Several Refinements to the -Gm Topology Using BipolarTransistors -- 9.12 The Effect of Parasitics on the Frequency of Oscillation -- 9.13 Large-Signal Nonlinearity in the Transistor -- 9.14 Bias Shifting During Startup -- 9.15 Colpitts Oscillator Amplitude -- 9.16 -Gm Oscillator Amplitude -- 9.17 Phase Noise.

9.17.1 Linear or Additive Phase Noise and Leeson's Formula.