Wafer-Level Testing and TestDuring Burn-In for Integrated Circuits -- Contents -- Preface -- Acknowledgements -- Chapter 1 Introduction -- 1.1 BACKGROUND -- 1.1.1 System-Level Design-for-Test and Test Scheduling for Core-Based SoCs -- 1.1.2 Wafer-Level Test During Burn-In -- 1.1.3 Scan Design -- 1.2 KEY DRIVERS FORWAFER-LEVEL TEST AND BURN-IN -- 1.2.1 Challenges Associated withWafer Sort -- 1.2.2 Emergence of KGDs -- 1.2.3 WLTBI: Industry Adoption and Challenges -- 1.3 WAFER-LEVEL TEST PLANNING FOR CORE-BASED SOCS -- 1.4 WAFER-LEVEL DEFECT SCREENING FOR MIXED-SIGNAL SOCS -- 1.5 WLTBI OF CORE-BASED SOCS -- 1.6 POWER MANAGEMENT FOR WLTBI -- 1.7 HOWTHIS BOOK IS ORGANIZED -- References -- Chapter 2 Wafer-Level Test and Burn-In: Industry Practices and Trends -- 2.1 OVERVIEW AND DEFINITIONS -- 2.2 STATUS OFWAFER-LEVEL TEST AND WLBI -- 2.2.1 Wafer-Level Burn-In -- 2.3 DOING BOTH WAFER-LEVEL TEST AND WAFER-LEVEL BURN IN -- 2.4 PRACTICAL MATTERS -- 2.4.1 Volumes Needed -- 2.4.2 Power per Die and perWafer -- 2.4.3 Types of Die That Can Be Tested and Burned-In -- 2.4.4 Functional Tests Versus Parametric Tests -- 2.4.5 Number of Contacts per Die -- 2.4.6 Number of Signal Channels Needed -- 2.4.7 Single-Pass Versus Multiple Pass -- 2.4.8 Maximum Force per Wafer -- 2.4.8 Maximum Force per Wafer -- 2.4.9 ContactMethod -- 2.4.10 Contact Life -- 2.4.11 Minimizing Costs for SDBs and Contactors -- 2.4.12 Bumped Wafers VersusWafers with Bond Pads -- 2.4.13 Pitch -- 2.4.14 Pad Size -- 2.4.15 Coplanarity -- 2.4.16 Background (Thinned) Wafers and Plastic-BackedWafers -- 2.4.17 More Than One Die Type on theWafer -- 2.4.18 Changing Cartridges -- 2.4.19 Test Electronics -- 2.4.20 Die Power and Shorted Die -- 2.4.21 Current per Die and perWafer -- 2.4.22 Voltage Levels Needed -- 2.4.23 Clock and Pattern Frequencies -- 2.4.24 WaferMaps and Binning -- 2.5 FUTURE PROJECTIONS.

References -- Chapter 3 Resource-Constrained Testing of Core-Based SoCs -- 3.1 DEFECT PROBABILITY ESTIMATION FOR EMBEDDED CORES -- 3.1.1 Unified Negative-BinomialModel for Yield Estimation -- 3.1.2 Procedure to Determine Core Defect Probabilities -- 3.2 TEST-LENGTH SELECTION FORWAFER-LEVEL TEST -- 3.2.1 Test-Length Selection Problem:PTLS -- 3.2.2 Efficient Heuristic Procedure -- 3.2.3 Greedy Heuristic Procedure -- 3.3 EXPERIMENTAL RESULTS -- 3.3.1 Approximation Error in PrS Due to Taylor Series Approximation -- 3.4 TEST DATA SERIALIZATION -- 3.4.1 Test-Length and TAM Optimization Problem:PTLTWS -- 3.4.2 Experimental Results:PTLTWS -- 3.4.3 Enumeration-Based TAMWidth and Test-Length Selection -- 3.4.4 TAMWidth and Test-Length Selection Based on Geometric Programming -- 3.4.5 Approximation Error in PrS -- 3.5 SUMMARY -- References -- Chapter 4 Defect Screening for "Big-D/Small-A"Mixed-Signal SoCs -- 4.1 TEST WRAPPER FOR ANALOG CORES -- 4.1.1 Analog Test Wrapper Modes -- 4.2 WAFER-LEVEL DEFECT SCREENING: MIXED-SIGNAL CORES -- 4.2.1 Signature Analysis: Mean-Signature-Based Correlation (MSBC) -- 4.2.2 Signature Analysis: Golden-Signature-Based Correlation (GSBC) -- 4.3 GENERIC COST MODEL -- 4.3.1 Correction Factors: Test Escapes and Yield Loss -- 4.3.2 Cost Model: Generic Framework -- 4.3.3 Overall Cost Components -- 4.4 COST MODEL: QUANTITATIVE ANALYSIS -- 4.4.1 Cost Model: Results for ASIC Chip K -- 4.4.2 Cost Model: Results Considering Failures Due to Both Digital and Mixed-Signal Cores -- 4.4.3 Cost Model: Results Considering Failure Distributions -- 4.5 SUMMARY -- 4.6 ACKNOWLEDGMENTS -- References -- Chapter 5 Wafer-Level Test During Burn-In: TestScheduling for Core-Based SOCs -- 5.1 CYCLE-ACCURATE POWER MODELING -- 5.1.1 Transitions in a Scan Chain -- 5.1.2 Transitions in Wrapper Chains -- 5.2 TEST SCHEDULING FOR WLTBI.

5.2.1 Graph-Matching-Based Approach for Test Scheduling -- 5.3 HEURISTIC PROCEDURE TO SOLVE PCORE ORDER -- 5.4 BASELINE METHODS -- 5.5 EXPERIMENTAL RESULTS -- 5.6 SUMMARY -- 5.7 ACKNOWLEDGMENTS -- References -- Chapter 6 Wafer-Level Test During Burn-In: Power Management by Test-Pattern Ordering -- 6.1 BACKGROUND: CYCLE-ACCURATE POWER MODELING -- 6.1.1 Scan-Chain Transition-Count Calculation -- 6.2 TEST-PATTERN ORDERING PROBLEM: PTPO -- 6.2.1 Computational Complexity of PTPO -- 6.3 HEURISTIC METHODS FOR TEST-PATTERN ORDERING -- 6.4 BASELINE APPROACHES -- 6.4.1 Baseline Method 1: Average Power Consumption -- 6.4.2 Baseline Method 2: Peak Power Consumption -- 6.5 EXPERIMENTAL RESULTS -- 6.6 SUMMARY -- References -- Chapter 7 Wafer-Level Test During Burn-In: Power Management by Test-Pattern Manipulation -- 7.1 MINIMUM-VARIATION X-FILL PROBLEM: PMV F -- 7.1.1 Metrics: Variation in Power Consumption During Test -- 7.1.2 Outline of ProposedMethod -- 7.2 FRAMEWORK TO CONTROL POWER VARIATION FOR WLTBI -- 7.2.1 Minimum-Variation X-Filling -- 7.2.2 Eliminating Capture-Power Violations -- 7.2.3 Test-Pattern Ordering for WLTBI -- 7.2.4 Complete Procedure -- 7.3 BASELINE APPROACHES -- 7.3.1 Baseline Method 1: Adjacent Fill -- 7.3.2 Baseline Method 2: 0-Fill -- 7.3.3 Baseline Method 3: 1-Fill -- 7.3.4 Baseline Method 4: ATPG-Compacted Test Sets -- 7.4 EXPERIMENTAL RESULTS -- 7.5 SUMMARY -- References -- Chapter 8 Conclusions -- 8.1 SUMMARY -- 8.2 FUTURE WORK -- 8.2.1 Integrated Test-Length and Test-Pattern Selection for Core-Based SoCs -- 8.2.2 Multiple Scan-Chain Design for WLTBI -- 8.2.3 Layout-Aware SoC Test Scheduling for WLTBI -- References -- List of Symbols -- List of Acronyms -- About the Authors -- Index.