Title page -- Copyright page -- Contents -- Preface -- Contributors -- 1: Low Power Multicore Processors for Embedded Systems -- 1.1 Multicore Chip with Highly Efficient Cores -- 1.2 SuperH™ RISC Engine Family (SH) Processor Cores -- 1.2.1 History of SH Processor Cores -- 1.2.2 Highly Efficient ISA -- 1.2.3 Asymmetric In-Order Dual-Issue Superscalar Architecture -- 1.3 SH-X: A Highly Efficient CPU Core -- 1.3.1 Microarchitecture Selections -- 1.3.2 Improved Superpipeline Structure -- 1.3.3 Branch Prediction and Out-of-Order Branch Issue -- 1.3.4 Low Power Technologies -- 1.3.5 Performance and Efficiency Evaluations -- 1.4 SH-X FPU: A Highly Efficient FPU -- 1.4.1 FPU Architecture of SH Processors -- 1.4.2 Implementation of SH-X FPU -- 1.4.3 Performance Evaluations with 3D Graphics Benchmark -- 1.5 SH-X2: Frequency and Efficiency Enhanced Core -- 1.5.1 Frequency Enhancement -- 1.5.2 Low Power Technologies -- 1.6 SH-X3: Multicore Architecture Extension -- 1.6.1 SH-X3 Core Specifications -- 1.6.2 Symmetric and Asymmetric Multiprocessor Support -- 1.6.3 Core Snoop Sequence Optimization -- 1.6.4 Dynamic Power Management -- 1.6.5 RP-1 Prototype Chip -- 1.6.6 RP-2 Prototype Chip -- 1.7 SH-X4: ISA and Address Space Extension -- 1.7.1 SH-X4 Core Specifications -- 1.7.2 Efficient ISA Extension -- 1.7.3 Address Space Extension -- 1.7.4 Data Transfer Unit -- 1.7.5 RP-X Prototype Chip -- References -- 2: Special-Purpose Hardware for Computational Biology -- 2.1 Molecular Dynamics Simulations on Graphics Processing Units -- 2.1.1 Molecular Mechanics Force Fields -- 2.1.2 Graphics Processing Units for MD Simulations -- 2.2 Special-Purpose Hardware and Network Topologies for MD Simulations -- 2.2.1 High-Throughput Interaction Subsystem -- 2.2.2 Hardware Description of the Flexible Subsystem -- 2.2.3 Performance and Conclusions.

2.3 Quantum MC Applications on Field-Programmable Gate Arrays -- 2.3.1 Energy Computation and WF Kernels -- 2.3.2 Hardware Architecture -- 2.3.3 PE and WF Computation Kernels -- 2.4 Conclusions and Future Directions -- References -- 3: Embedded GPU Design -- 3.1 Introduction -- 3.2 System Architecture -- 3.3 Graphics Modules Design -- 3.3.1 RISC Processor -- 3.3.2 Geometry Processor -- 3.3.3 Rendering Engine -- 3.4 System Power Management -- 3.4.1 Multiple Power-Domain Management -- 3.4.2 Power Management Unit -- 3.5 Implementation Results -- 3.5.1 Chip Implementation -- 3.5.2 Comparisons -- 3.6 Conclusion -- References -- 4: Low-Cost VLSI Architecture for Random Block-Based Access of Pixels in Modern Image Sensors -- 4.1 Introduction -- 4.2 The DVP Interface -- 4.3 The iBRIDGE-BB Architecture -- 4.3.1 Configuring the iBRIDGE-BB -- 4.3.2 Operation of the iBRIDGE-BB -- 4.3.3 Description of Internal Blocks -- 4.4 Hardware Implementation -- 4.4.1 Verification in Field-Programmable Gate Array -- 4.4.2 Application in Image Compression -- 4.4.3 Application-Specific Integrated Circuit (ASIC) Synthesis and Performance Analysis -- 4.5 Conclusion -- Acknowledgments -- References -- 5: Embedded Computing Systems on FPGAs -- 5.1 FPGA Architecture -- 5.2 FPGA Configuration Technology -- 5.2.1 Traditional SRAM-Based FPGAs -- 5.2.2 Flash-Based FPGAs -- 5.3 Software Support -- 5.3.1 Synthesis and Design Tools -- 5.3.2 OSs Support -- 5.4 Final Summary of Challenges and Opportunities for Embedded Computing Design on FPGAs -- References -- 6: FPGA-Based Emulation Support for Design Space Exploration -- 6.1 Introduction -- 6.2 State of the Art -- 6.2.1 FPGA-Only Emulation Techniques -- 6.2.2 FPGA-Based Cosimulation Techniques -- 6.2.3 FPGA-Based Emulation for DSE Purposes: A Limiting Factor.

6.3 A Tool for Energy-Aware FPGA-Based Emulation: The MADNESS Project Experience -- 6.3.1 Models for Prospective ASIC Implementation -- 6.3.2 Performance Extraction -- 6.4 Enabling FPGA-Based DSE: Runtime-Reconfigurable Emulators -- 6.4.1 Enabling Fast NoC Topology Selection -- 6.4.2 Enabling Fast ASIP Configuration Selection -- 6.5 Use Cases -- 6.5.1 Hardware Overhead Due to Runtime Configurability -- References -- 7: FPGA Coprocessing Solution for Real-Time Protein Identification Using Tandem Mass Spectrometry -- 7.1 Introduction -- 7.2 Protein Identification by Sequence Database Searching Using MS/MS Data -- 7.3 Reconfigurable Computing Platform -- 7.4 FPGA Implementation of the MS/MS Search Engine -- 7.4.1 Protein Database Encoding -- 7.4.2 Overview of the Database Search Engine -- 7.4.3 Search Processor Architecture -- 7.4.4 Performance -- 7.5 Summary -- Acknowledgments -- References -- 8: Real-Time Configurable Phase-Coherent Pipelines -- 8.1 Introduction and Purpose -- 8.1.1 Efficiency of Pipelined Computation -- 8.1.2 Direct Datapath (Systolic Array) -- 8.1.3 Custom Soft Processors -- 8.1.4 Implementation Framework (e.g., C to VHDL) -- 8.1.5 Multicore -- 8.1.6 Pipeline Data-Feeding Considerations -- 8.1.7 Purpose of Configurable Phase-Coherent Pipeline Approach -- 8.2 History and Related Methods -- 8.2.1 Issues in Tracking Data through Pipelines -- 8.2.2 Decentralized Tag-Based Control -- 8.2.3 Tags in Instruction Pipelines -- 8.2.4 Similar Techniques in Nonpipelined Applications -- 8.2.5 Development-Friendly Approach -- 8.3 Implementation Framework -- 8.3.1 Dynamically Configurable Pipeline -- 8.3.2 Phase Tag Control -- 8.3.3 Phase-Coherent Resource Allocation -- 8.4 Prototype Implementation -- 8.4.1 Coordinate Conversion and Regridding -- 8.4.2 Experimental Setup -- 8.4.3 Experimental Results -- 8.5 Assessment Compared with Related Methods.

References -- 9: Low Overhead Radiation Hardening Techniques for Embedded Architectures -- 9.1 Introduction -- 9.2 Recently Proposed SEU Tolerance Techniques -- 9.2.1 Radiation Hardened Latch Design -- 9.2.2 Radiation-Hardened Circuit Design Using Differential Cascode Voltage Swing Logic -- 9.2.3 SEU Detection and Correction Using Decoupled Ground Bus -- 9.3 Radiation-Hardened Reconfigurable Array with Instruction Rollback -- 9.3.1 Overview of the MORA Architecture -- 9.3.2 Single-Cycle Instruction Rollback -- 9.3.3 MORA RC with Rollback Mechanism -- 9.3.4 Impact of the Rollback Scheme on Throughput of the Architecture -- 9.3.5 Comparison of Proposed Schemes with Competing SEU Hardening Schemes -- 9.4 Conclusion -- References -- 10: Hybrid Partially Adaptive Fault-Tolerant Routing for 3D Networks-on-Chip -- 10.1 Introduction -- 10.2 Related Work -- 10.3 Proposed 4NP-First Routing Scheme -- 10.3.1 3D Turn Models -- 10.3.2 4NP-First Overview -- 10.3.3 Turn Restriction Checks -- 10.3.4 Prioritized Valid Path Selection -- 10.3.5 4NP-First Router Implementation -- 10.4 Experiments -- 10.4.1 Experimental Setup -- 10.4.2 Comparison with Existing FT Routing Schemes -- 10.5 Conclusion -- References -- 11: Interoperability in Electronic Systems -- 11.1 Interoperability -- 11.2 The Basis for Interoperability: The OSI Model -- 11.3 Hardware -- 11.4 Firmware -- 11.5 Partitioning the System -- 11.6 Examples of Interoperable Systems -- 12: Software Modeling Approaches for Presilicon System Performance Analysis -- 12.1 Introduction -- 12.2 Methodologies -- 12.2.1 High-Level Software Description -- 12.2.2 Transaction Trace File -- 12.2.3 Stochastic Traffic Generator -- 12.3 Results -- 12.3.1 Audio Power Consumption: High-Level Software Description -- 12.3.2 Cache Analysis: Transaction Trace File -- 12.3.3 GPU Traffic Characterization: Stochastic Traffic Generator.

12.4 Conclusion -- References -- 13: Advanced Encryption Standard (AES) Implementation in Embedded Systems -- 13.1 Introduction -- 13.2 Finite Field -- 13.2.1 Addition in Finite Field -- 13.2.2 Multiplication in Finite Field -- 13.3 The AES -- 13.3.1 Shift Rows/Inverse Shift Rows -- 13.3.2 Byte Substitution and Inverse Byte Substitution -- 13.3.3 Mix Columns/Inverse Mix Columns Steps -- 13.3.4 Key Expansion and Add Round Key Step -- 13.4 Hardware Implementations for AES -- 13.4.1 Composite Field Arithmetic S-BOX -- 13.4.2 Very High Speed AES Design -- 13.5 High-Speed AES Encryptor with Efficient Merging Techniques -- 13.5.1 The Integrated-BOX -- 13.5.2 Key Expansion Unit -- 13.5.3 The AES Encryptor with the Merging Technique -- 13.5.4 Results and Comparison -- 13.6 Conclusion -- References -- 14: Reconfigurable Architecture for Cryptography over Binary Finite Fields -- 14.1 Introduction -- 14.2 Background -- 14.2.1 Elliptic Curve Cryptography -- 14.2.2 Advanced Encryption Standard -- 14.2.3 Random Number Generators -- 14.3 Reconfigurable Processor -- 14.3.1 Processing Unit for Elliptic Curve Cryptography -- 14.3.2 Processing Unit for the AES -- 14.3.3 Random Number Generator -- 14.3.4 Microinstructions and Access Arbiter -- 14.4 Results -- 14.4.1 Individual Components -- 14.4.2 Complete Processor Evaluation -- 14.5 Conclusions -- References -- Index.