Title Page -- Contents -- Preface -- PART 1. ELEMENTS OF A BASIC ARCHITECTURE -- Chapter 1. Introduction -- 1.1. Historical background -- 1.1.1. Automations and mechanical calculators -- 1.1.2. From external program to stored program -- 1.1.3. The different generations -- 1.2. Introduction to internal operation -- 1.2.1. Communicating with the machine -- 1.2.2. Carrying out the instructions -- 1.3. Future prospects -- Chapter 2. The Basic Modules -- 2.1. Memory -- 2.1.1. Definitions -- 2.1.2. A few elements of technology -- 2.2. The processor -- 2.2.1. Functional units -- 2.2.2. Processor registers -- 2.2.3. The elements of the processing unit -- 2.2.4. The elements of the control unit -- 2.2.5. The address calculation unit -- 2.3. Communication between modules -- 2.3.1. The PCI bus -- Chapter 3. The Representation of Information -- 3.1. Review -- 3.1.1. Base 2 -- 3.1.2. Binary, octal and hexadecimal representations -- 3.2. Number representation conventions -- 3.2.1. Integers -- 3.2.2. Real numbers -- 3.2.3. An example of a floating-point representation, the IEEE-754 standard -- 3.2.4. Dynamic range and precision -- 3.2.5. Implementation -- 3.2.6. Extensions of the IEEE-754 standard -- 3.3. Character representation -- 3.3.1. 8-bit representation -- 3.3.2. Modern representations -- 3.4. Exercises -- PART 2. PROGRAMMING MODEL AND OPERATION -- Chapter 4. Instructions -- 4.1. Programming model -- 4.1.1. The registers of the I8086 -- 4.1.2. Address construction and addressing modes -- 4.2. The set of instructions -- 4.2.1. Movement instructions -- 4.2.2. Arithmetic and logic instructions -- 4.2.3. Shift instructions -- 4.2.4. Branching -- 4.2.5. Other instructions -- 4.3. Programming examples -- 4.4. From assembly language to basic instructions -- 4.4.1. The assembler -- 4.4.2. The assembly phases -- 4.4.3. The linker.

4.4.4. When to program in assembly language -- Chapter 5. The Processor -- 5.1. The control bus -- 5.1.1. Reset line -- 5.1.2. Hold line -- 5.1.3. Wait control line -- 5.1.4. Interrupt lines -- 5.1.5. Conceptual diagram -- 5.2. Execution of an instruction: an example -- 5.2.1. Execution of the instruction -- 5.2.2. Timing diagram -- 5.3. Sequencer composition -- 5.3.1. Traditional synthesis methods -- 5.3.2. Microprogramming -- 5.4. Extensions -- 5.4.1. Coprocessors -- 5.4.2. Vector extensions -- 5.4.3. DSP and GPU -- 5.5. Exercise -- Chapter 6. Inputs and Outputs -- 6.1. Examples -- 6.1.1. Example: controlling a thermocouple -- 6.1.2. Example: serial terminal connection -- 6.2. Design and addressing of EU -- 6.2.1. Design of exchange units -- 6.2.2. Exchange unit addressing -- 6.3. Exchange modes -- 6.3.1. The polling exchange mode -- 6.3.2. Direct memory access -- 6.3.3. Interrupts -- 6.4. Handling interrupts -- 6.4.1. Operating principle -- 6.4.2. Examples -- 6.4.3. Software interrupts -- 6.4.4. Masking and unmasking interrupts -- 6.4.5. Interrupt priorities or levels -- 6.4.6. Similar mechanisms -- 6.5. Exercises -- PART 3. MEMORY HIERARCHY -- Chapter 7. Memory -- 7.1. The memory resource -- 7.2. Characteristics -- 7.3. Memory hierarchy -- 7.3.1. Principle of locality -- 7.3.2. Hierarchy organization and management -- 7.3.3. Definitions and performance -- 7.4. Memory size and protection -- 7.5. Segmentation -- 7.5.1. Using segment registers: an example -- 7.5.2. Using segment descriptors -- 7.6. Paging -- 7.7. Memory interleaving and burst mode -- 7.7.1. C-access -- 7.7.2. S-access -- 7.7.3. Burst mode -- 7.7.4. Prefetch buffers -- 7.8. Protections, example of the I386 -- Chapter 8. Caches -- 8.1. Cache memory -- 8.1.1. Operating principle and architectures -- 8.1.2. Cache memory operation -- 8.1.3. Cache design -- 8.2. Replacement algorithms.

8.2.1. The LRU method -- 8.2.2. The case of several levels of cache -- 8.2.3. Performance and simulation -- Chapter 9. Virtual Memory -- 9.1. General concept -- 9.1.1. Operation -- 9.1.2. Accessing information -- 9.1.3. Address translation -- 9.2. Rules of the access method -- 9.2.1. Page fault -- 9.2.2. Multi-level paging -- 9.2.3. Service information, protection and access rights -- 9.2.4. Page size -- 9.3. Example of the execution of a program -- 9.3.1. Introducing the translation cache -- 9.3.2. Execution -- 9.3.3. Remarks -- 9.4. Example of two-level paging -- 9.4.1. Management -- 9.4.2. Handling service bits -- 9.4.3. Steps in the access to information -- 9.5. Paged segmentation -- 9.5.1. 36-bit extensions -- 9.6. Exercise -- 9.7. Documentation excerpts -- 9.7.1. Introduction to the MMU -- 9.7.2. Description of the TLB -- 9.7.3. TLB features -- PART 4. PARALLELISM AND PERFORMANCE ENHANCEMENT -- Chapter 10. Pipeline Architectures -- 10.1. Motivations and ideas -- 10.1.1. RISC machines -- 10.1.2. Principle of operation -- 10.1.3. Cost of the pipeline architecture -- 10.2. Pipeline management problems -- 10.2.1. Structural hazards -- 10.2.2. Dependency conflicts -- 10.2.3. Branches -- 10.3. Handling branches -- 10.3.1. Delayed branches and software handling -- 10.3.2. Branch predictions -- 10.3.3. Branch target buffer -- 10.3.4. Global prediction -- 10.3.5. Examples -- 10.4. Interrupts and exceptions -- 10.4.1. Interrupts -- 10.4.2. Traps and faults -- Chapter 11. Example of an Architecture -- 11.1. Presentation -- 11.1.1. Description of the pipeline -- 11.1.2. The instruction set -- 11.1.3. Instruction format -- 11.2. Executing an instruction -- 11.2.1. Reading and decoding an instruction -- 11.2.2. Memory read -- 11.2.3. Memory write operations -- 11.2.4. Register to register operations -- 11.2.5. Conditional branching.

11.2.6. Instruction with immediate addressing -- 11.3. Conflict resolution in the DLX -- 11.3.1. Forwarding techniques -- 11.3.2. Handling branches -- 11.4. Exercises -- Chapter 12. Caches in a Multiprocessor Environment -- 12.1. Cache coherence -- 12.1.1. Examples -- 12.1.2. The elements to consider -- 12.1.3. Definition of coherence -- 12.1.4. Methods -- 12.2. Examples of snooping protocols -- 12.2.1. The MSI protocol -- 12.2.2. The MEI protocol -- 12.2.3. The MESI protocol -- 12.2.4. The MOESI protocol -- 12.3. Improvements -- 12.4. Directory-based coherence protocols -- 12.5. Consistency -- 12.5.1. Consistency and coherence -- 12.5.2. Notations -- 12.5.3. Atomic consistency -- 12.5.4. Sequential consistency -- 12.5.5. Causal consistency -- 12.5.6. Weak consistency -- 12.6. Exercises -- Chapter 13. Superscalar Architectures -- 13.1. Superscalar architecture principles -- 13.1.1. Hazards -- 13.2. Seeking solutions -- 13.2.1. Principles -- 13.2.2. Example -- 13.3. Handling the flow of instructions -- 13.3.1. Principle of scoreboarding -- 13.3.2. Scoreboarding implementation -- 13.3.3. Detailed example -- 13.3.4. Comments on precedence constraints -- 13.3.5. Principle of the Tomasulo algorithm -- 13.3.6. Detailed example -- 13.3.7. Loop execution and WAW hazards -- 13.4. VLIW architectures -- 13.4.1. Limits of superscalar architectures -- 13.4.2. VLIW architectures -- 13.4.3. Predication -- 13.5. Exercises -- PART 5. APPENDICES -- Appendix A. Hints and Solutions -- A1.1. The representation of information -- A1.2. The processor -- A1.3. Inputs and outputs -- A1.4. Virtual memory -- A1.5. Pipeline architectures -- A1.6. Caches in a multiprocessor environment -- A1.7. Superscalar architectures -- Appendix B. Programming Models -- A2.1. Instruction coding in the I8086 -- A2.2. Instruction set of the DLX architecture.

A2.2.1. Operations on floating-point numbers -- A2.2.2. Move operations -- A2.2.3. Arithmetic and logic operations -- A2.2.4. Branches -- Bibliography -- Index.