CMOS Sigma-Delta Converters : Practical Design Guide.
Title:
CMOS Sigma-Delta Converters : Practical Design Guide.
Author:
de la Rosa, José M.
ISBN:
9781118569221
Personal Author:
Edition:
1st ed.
Physical Description:
1 online resource (428 pages)
Series:
Wiley - IEEE
Contents:
Cover -- Tilte Page -- Copyright -- Contents -- List of Abbreviations -- Preface -- Acknowledgements -- Chapter 1 Introduction to ΣΔ Modulators: Basic Concepts and Fundamentals -- 1.1 Basics of A/D Conversion -- 1.1.1 Sampling -- 1.1.2 Quantization -- 1.1.3 Quantization White Noise Model -- 1.1.4 Noise Shaping -- 1.2 Basics of Sigma-Delta Modulators -- 1.2.1 Topology of ΣΔ ADCs -- 1.2.2 Signal Processing in ΣΔMs -- 1.2.3 Performance Metrics of ΣΔMs -- 1.2.4 Performance Enhancement of ΣΔMs -- 1.3 Classification of ΣΔ Modulators -- 1.4 Single-Loop ΣΔ Modulators -- 1.4.1 Second-Order ΣΔM -- 1.4.2 High-Order ΣΔMs -- 1.5 Cascade ΣΔ Modulators -- 1.6 Multibit ΣΔ Modulators -- 1.6.1 Influence of Multibit DAC Errors -- 1.6.2 DEM Techniques -- 1.6.3 Dual Quantization -- 1.7 Band-Pass ΣΔ Modulators -- 1.7.1 The z→−z2 LP-BP Transformation -- 1.7.2 BP-ΣΔMs with Optimized NTF -- 1.8 Continuous-Time ΣΔ Modulators -- 1.8.1 DT-CT Transformation of ΣΔMs -- 1.8.2 Direct Synthesis of CT-ΣΔMs -- 1.9 Summary -- References -- Chapter 2 Circuits and Errors: Systematic Analysis and Practical Design Issues -- 2.1 Nonidealities in Switched-Capacitor ΣΔ Modulators -- 2.2 Finite Amplifier Gain in SC-ΣΔMs -- 2.3 Capacitor Mismatch in SC-ΣΔMs -- 2.4 Integrator Settling Error in SC-ΣΔMs -- 2.4.1 Behavioral Model for the Integrator Settling -- 2.4.2 Linear Effect of Finite Amplifier Gain-Bandwidth Product -- 2.4.3 Nonlinear Effect of Finite Amplifier Slew Rate -- 2.4.4 Effect of Finite Switch On-Resistance -- 2.5 Circuit Noise in SC-ΣΔMs -- 2.6 Clock Jitter in SC-ΣΔMs -- 2.7 Sources of Distortion in SC-ΣΔMs -- 2.7.1 Nonlinear Amplifier Gain -- 2.7.2 Nonlinear Switch On-Resistance -- 2.8 Nonidealities in Continuous-Time ΣΔ Modulators -- 2.9 Clock Jitter in CT-ΣΔMs -- 2.9.1 Jitter in Return-to-Zero DACs.
2.9.2 Jitter in NonReturn-to-Zero DACs -- 2.9.3 Jitter in Switched-Capacitor DACs -- 2.10 Excess Loop Delay in CT-ΣΔMs -- 2.11 Quantizer Metastability in CT-ΣΔMs -- 2.12 Finite Amplifier Gain in CT-ΣΔMs -- 2.13 Time-Constant Error in CT-ΣΔMs -- 2.14 Finite Integrator Dynamics in CT-ΣΔMs -- 2.15 Circuit Noise in CT-ΣΔMs -- 2.16 Sources of Distortion in CT-ΣΔMs -- 2.16.1 Nonlinearities in the Front-End Integrator -- 2.16.2 Intersymbol Interference in the Feedback DAC -- 2.17 Case Study: High-Level Sizing of a ΣΔM -- 2.18 Summary -- References -- Chapter 3 Behavioral Modeling and High-Level Simulation -- 3.1 Systematic Design Methodology of ΣΔ Modulators -- 3.1.1 System Partitioning and Abstraction Levels -- 3.1.2 Sizing Process -- 3.2 Simulation Approaches for the High-Level Evaluation of ΣΔMs -- 3.2.1 Alternatives to Transistor-Level Simulation -- 3.2.2 Event-Driven Behavioral Simulation Technique -- 3.2.3 Programming Languages and Behavioral Modeling Platforms -- 3.3 Implementing ΣΔM Behavioral Models -- 3.3.1 From Circuit Analysis to Computational Algorithms -- 3.3.2 Time-Domain versus Frequency-Domain Behavioral Models -- 3.3.3 Implementing Time-Domain Behavioral Models in MATLAB -- 3.3.4 Building Time-Domain Behavioral Models as SIMULINK C-MEX S-Functions -- 3.4 Efficient Behavioral Modeling of ΣΔM Building Blocks using C-MEX S-Functions -- 3.4.1 Modeling of SC Integrators using S-Functions -- 3.4.2 Modeling of CT Integrators using S-Functions -- 3.4.3 Behavioral Modeling of Quantizers using S-Functions -- 3.5 SIMSIDES: A SIMULINK-Based Behavioral Simulator for ΣΔMs -- 3.5.1 Model Libraries Included in SIMSIDES -- 3.5.2 Structure of SIMSIDES and User Interface -- 3.6 Using SIMSIDES for the High-Level Sizing and Verification of ΣΔMs -- 3.6.1 SC Second-Order Single-Bit ΣΔM -- 3.6.2 CT Fifth-Order Cascade 3-2 Multibit ΣΔM.
3.7 Summary -- References -- Chapter 4 Circuit-Level Design, Implementation, and Verification -- 4.1 Macromodeling ΣΔMs -- 4.1.1 SC Integrator Macromodel -- 4.1.2 CT Integrator Macromodel -- 4.1.3 Nonlinear OTA Transconductor -- 4.1.4 Embedded Flash ADC Macromodel -- 4.1.5 Feedback DAC Macromodel -- 4.1.6 Examples of ΣΔM Macromodels -- 4.2 Including Noise in Transient Electrical Simulations of ΣΔMs -- 4.2.1 Generating and Injecting Noise Data Sequences in HSPICE -- 4.2.2 Analyzing the Impact of Main Noise Sources in SC Integrators -- 4.2.3 Generating and Injecting Flicker Noise Sources in Electrical Simulations -- 4.2.4 Test Bench to Include Noise in the Simulation of ΣΔMs -- 4.3 Processing ΣΔM Output Results of Electrical Simulations -- 4.4 Design Considerations and Simulation Test Benches of ΣΔM Basic Building Blocks -- 4.4.1 Design Considerations of CMOS Switches -- 4.4.2 Design Considerations of Operational Amplifiers -- 4.4.3 Design Considerations of Transconductors -- 4.4.4 Design Considerations of Comparators -- 4.4.5 Design Considerations of Current-Steering DACs -- 4.5 Auxiliary ΣΔM Building Blocks -- 4.5.1 Clock-Phase Generators -- 4.5.2 Generation of Common-Mode Voltage, Reference Voltage, and Bias Currents -- 4.5.3 Additional Digital Logic -- 4.6 Layout Design, Floorplanning, and Practical Issues -- 4.6.1 Layout Floorplanning -- 4.6.2 I/O Pad Ring -- 4.6.3 Importance of Layout Verification and Catastrophic Failures -- 4.7 Chip Package, Test PCB, and Experimental Set-Up -- 4.7.1 Bonding Diagram and Package -- 4.7.2 Test PCB -- 4.7.3 Experimental Test Set-Up -- 4.8 Summary -- References -- Chapter 5 Frontiers of ΣΔ Modulators: Trends and Challenges -- 5.1 Overview of the State of the Art on ΣΔMs -- 5.1.1 DR-versus-Bw Conversion Region -- 5.1.2 Conversion Energy and Figures of Merit.
5.2 Empirical and Statistical Analysis of State-of-the-Art ΣΔMs -- 5.2.1 SC versus CT State-of-the-Art ΣΔMs -- 5.2.2 Gm-C versus Active-RC State-of-the-Art CT-ΣΔMs -- 5.2.3 Technology Used in State-of-the-Art ΣΔMs -- 5.2.4 Single-Loop versus Cascade State-of-the-Art ΣΔMs -- 5.2.5 Single-Bit versus Multibit State-of-the-Art ΣΔMs -- 5.2.6 Low-Pass versus Band-Pass State-of-the-Art ΣΔMs -- 5.3 Cutting-Edge ΣΔM Architectures and Techniques -- 5.3.1 SMASH ΣΔM Architectures -- 5.3.2 Hybrid ΣΔMs -- 5.3.3 Multirate ΣΔMs -- 5.3.4 Multibit ΣΔMs with Time-Coded Quantization -- 5.3.5 Mostly Digital ΣΔMs -- 5.3.6 Adaptive/Reconfigurable ΣΔMs -- 5.3.7 Ultra-High-Speed CT-ΣΔMs for RF Digitization -- 5.4 Classification of State-of-the-Art References -- 5.5 Summary -- References -- A SIMSIDES User Guide -- A.1 Getting Started: Installing and Running SIMSIDES -- A.2 Building and Editing ΣΔM Architectures in SIMSIDES -- A.3 Analyzing ΣΔMs in SIMSIDES -- A.4 Example -- A.5 Getting Help -- B SIMSIDES Block Libraries and Models -- B.1 Overview of SIMSIDES Libraries -- B.2 Ideal Libraries -- B.2.1 Ideal Integrators -- B.2.2 Ideal Resonators -- B.2.3 Ideal Quantizers -- B.2.4 Ideal D/A Converters -- B.3 Real SC Building-Block Libraries -- B.3.1 Real SC Integrators -- B.3.2 Real SC Resonators -- B.4 Real SI Building-Block Libraries -- B.4.1 Real SI Integrators -- B.4.2 Real SI Resonators -- B.4.3 SI Errors and Model Parameters -- B.5 Real CT Building-Block Libraries -- B.5.1 Real CT Integrators -- B.5.2 Real CT Resonators -- B.6 Real Quantizers and Comparators -- B.7 Real D/A Converters -- B.8 Auxiliary Blocks -- Index.
Abstract:
A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a practical guide to their design in nano-scale CMOS for optimal performance. This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations − going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues - from high-level behavioural modelling in MATLAB/SIMULINK, to circuit-level implementation in Cadence Design FrameWork II. As well as being a comprehensive reference to the theory, the book is also unique in that it gives special importance on practical issues, giving a detailed description of the different steps that constitute the whole design flow of sigma-delta ADCs. The book begins with an introductory survey of sigma-delta modulators, their fundamentals architectures and synthesis methods covered in Chapter 1. In Chapter 2, the effect of main circuit error mechanisms is analysed, providing the necessary understanding of the main practical issues affecting the performance of sigma-delta modulators. The knowledge derived from the first two chapters is presented in the book as an essential part of the systematic top-down/bottom-up synthesis methodology of sigma-delta modulators described in Chapter 3, where a time-domain behavioural simulator named SIMSIDES is described and applied to the high-level design and verification of sigma-delta ADCs. Chapter 4 moves farther down from system-level to the circuit and physical level, providing a number of design recommendations and practical recipes to complete the design flow of sigma-delta modulators. To conclude the book, Chapter 5 gives an overview of the
state-of-the-art sigma-delta ADCs, which are exhaustively analysed in order to extract practical design guidelines and to identify the incoming trends, design challenges as well as practical solutions proposed by cutting-edge designs. Offers a complete survey of sigma-delta modulator architectures from fundamentals to state-of-the art topologies, considering both switched-capacitor and continuous-time circuit implementations Gives a systematic analysis and practical design guide of sigma-delta modulators, from a top-down/bottom-up perspective, including mathematical models and analytical procedures, behavioural modeling in MATLAB/SIMULINK, macromodeling, and circuit-level implementation in Cadence Design FrameWork II, chip prototyping, and experimental characterization. Systematic compilation of cutting-edge sigma-delta modulators Complete description of SIMSIDES, a time-domain behavioural simulator implemented in MATLAB/SIMULINK Plenty of examples, case studies, and simulation test benches, covering the different stages of the design flow of sigma-delta modulators A number of electronic resources, including SIMSIDES, the statistical data used in the state-of-the-art survey, as well as many design examples and test benches are hosted on a companion website Essential reading for Researchers and electronics engineering practitioners interested in the design of high-performance data converters integrated in nanometer CMOS technologies; mixed-signal designers.
Local Note:
Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2017. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries.
Genre:
Electronic Access:
Click to View