Contents -- Preface -- Chapter 1. Introduction: Mixed Analog-Digital Chips -- 1.1 The Role and Place of Modern Mixed Analog-Digital Chips -- 1.2 Advantages of Mixing Analog and Digital Circuits on the Same Chip -- 1.3 Applications of MAD Chips -- 1.4 Obstacles in the Design of MAD Chips -- 1.5 The Aim and Contents of This Book -- Chapter 2. The MOSFET: Introduction and Qualitative View -- 2.1 Introduction -- 2.2 MOS Transistor Structure -- 2.3 Assumptions about Terminal Voltages Currents and Temperature -- 2.4 A Qualitative Description of MOSFET Operation -- 2.4.1 Effect of VGS: Level of Inversion -- 2.4.2 Effect of VSB: The Body Effect -- 2.4.3 Effect of VDS: Drain Current -- 2.5 A Fluid Dynamical Analog -- 2.6 Complete Set of Characteristics -- 2.7 Form of Functional lD-VGS Dependence: Practical Limits for Regions of Inversion -- 2.8 Factors Affecting the Extrapolated Threshold Voltage -- 2.9 Other Factors Affecting the Drain Current -- Chapter 3. MOSFET DC Modeling -- 3.1 Introduction -- 3.2 DC Model for Weak and for Strong Inversion -- 3.2.1 The Current Equations -- 3.2.2 Model Parameters Influenced by the Body Effect -- 3.2.3 Origin and Validity of the Model -- 3.3 Drain versus Source -- 3.4 Symmetric Models -- 3.5 General Models and Moderate Inversion -- 3.6 Mobility Dependence on Gate and Substrate Bias -- 3.7 Temperature Effects -- 3.8 Small-Dimension Effects -- 3.9 Breakdown -- 3.10 The pMOS Transistor -- 3.11 Device Symbols -- 3.12 Model Accuracy Parameter Extraction and Computer Simulation -- Chapter 4. MOSFET Small-Signal Modeling -- 4.1 Introduction -- 4.2 Small-Signal Conductance Parameters -- 4.3 Expressions for Small-Signal Conductance Parameters in Weak and in Strong Inversion -- 4.3.1 Gate Transconductance -- 4.3.2 Body Transconductance -- 4.3.3 Drain-Source Conductance.

4.3.4 Drain-Substrate Conductance -- 4.3.5 Examples -- 4.3.6 Small-Signal Parameters in the Presence of Second-Order Effects -- 4.4 Capacitance Parameters -- 4.4.1 Extrinsic Capacitances -- 4.4.2 Intrinsic Capacitances in Weak and in Strong Inversion -- 4.5 Intrinsic Cutoff Frequency and Limits of Model Validity -- 4.6 The Transistor at Very High Frequencies -- 4.6.1 Extrinsic Parasitic Resistances -- 4.6.2 Intrinsic Nonquasi-static Effects -- 4.7 Noise -- 4.7.1 Introductory Remarks -- 4.7.2 MOS Transistor Noise -- 4.8 General Models and Moderate Inversion -- 4.9 Parameter Extraction for Accurate Small-Signal Modeling -- 4.10 Requirements for Good CAD Models -- Chapter 5. Technology and Available Circuit Components -- 5.1 Introduction -- 5.2 The n-Well CMOS Process -- 5.2.1 Basic Fabrication Steps and MOS Transistor Structures -- 5.2.2 Capacitors -- 5.2.3 Resistors -- 5.2.4 Inductors -- 5.2.5 Bipolar Transistors -- 5.2.6 Interconnects -- 5.2.7 Electrical Parameters -- 5.2.8 Input Protection -- 5.2.9 Latch-up -- 5.3 BiCMOS Processes -- 5.3.1 Adding High-Performance Bipolar Transistors to CMOS -- 5.3.2 Bipolar Transistor Models -- 5.4 Other Silicon Processes -- 5.5 Sensors -- 5.6 Trimming -- 5.7 Tolerance and Matching of Electrical Parameters -- 5.8 Chip Size and Yield -- 5.9 The Influence of Pads and Package -- Chapter 6. Layout -- 6.1 Introduction -- 6.2 Relation of Fabricated Transistors to Layout -- 6.3 Transistor Geometry and Layout -- 6.4 Layout for Device Matching and Precision Parameter Ratios -- 6.4.1 Capacitor Layout -- 6.4.2 Resistor Layout -- 6.4.3 Transistor Layout -- 6.4.4 A Collection of Rules for Good Matching -- 6.5 Layout for Interference Reduction -- 6.6 Integrated-Circuit Design -- Appendix A Additional MOS Transistor Modeling Information.

Appendix B A Set of Benchmark Tests for Evaluating MOSFET Models for Analog Design -- Appendix C A Sample Spice Input File -- Index.