Event-Based Neuromorphic Systems.
Title:
Event-Based Neuromorphic Systems.
Author:
Liu, Shih-Chii.
ISBN:
9781118927632
Personal Author:
Edition:
1st ed.
Physical Description:
1 online resource (442 pages)
Contents:
EVENT-BASED NEUROMORPHIC SYSTEMS -- Contents -- List of Contributors -- Foreword -- Acknowledgments -- List of Abbreviations and Acronyms -- 1 Introduction -- 1.1 Origins and Historical Context -- 1.2 Building Useful Neuromorphic Systems -- References -- Part I Understanding Neuromorphic Systems -- 2 Communication -- 2.1 Introduction -- 2.2 Address-Event Representation -- 2.2.1 AER Encoders -- 2.2.2 Arbitration Mechanisms -- 2.2.3 Encoding Mechanisms -- 2.2.4 Multiple AER Endpoints -- 2.2.5 Address Mapping -- 2.2.6 Routing -- 2.3 Considerations for AER Link Design -- 2.3.1 Trade-off: Dynamic or Static Allocation -- 2.3.2 Trade-off: Arbitered Access or Collisions? -- 2.3.3 Trade-off: Queueing versus Dropping Spikes -- 2.3.4 Predicting Throughput Requirements -- 2.3.5 Design Trade-offs -- 2.4 The Evolution of AER Links -- 2.4.1 Single Sender, Single Receiver -- 2.4.2 Multiple Senders, Multiple Receivers -- 2.4.3 Parallel Signal Protocol -- 2.4.4 Word-Serial Addressing -- 2.4.5 Serial Differential Signaling -- 2.5 Discussion -- References -- 3 Silicon Retinas -- 3.1 Introduction -- 3.2 Biological Retinas -- 3.3 Silicon Retinas with Serial Analog Output -- 3.4 Asynchronous Event-Based Pixel Output Versus Synchronous Frames -- 3.5 AER Retinas -- 3.5.1 Dynamic Vision Sensor -- 3.5.2 Asynchronous Time-Based Image Sensor -- 3.5.3 Asynchronous Parvo-Magno Retina Model -- 3.5.4 Event-Based Intensity-Coding Imagers (Octopus and TTFS) -- 3.5.5 Spatial Contrast and Orientation Vision Sensor (VISe) -- 3.6 Silicon Retina Pixels -- 3.6.1 DVS Pixel -- 3.6.2 ATIS Pixel -- 3.6.3 VISe Pixel -- 3.6.4 Octopus Pixel -- 3.7 New Specifications for Silicon Retinas -- 3.7.1 DVS Response Uniformity -- 3.7.2 DVS Background Activity -- 3.7.3 DVS Dynamic Range -- 3.7.4 DVS Latency and Jitter -- 3.8 Discussion -- References -- 4 Silicon Cochleas -- 4.1 Introduction.
4.2 Cochlea Architectures -- 4.2.1 Cascaded 1D -- 4.2.2 Basic 1D Silicon Cochlea -- 4.2.3 2D Architecture -- 4.2.4 The Resistive (Conductive) Network -- 4.2.5 The BM Resonators -- 4.2.6 The 2D Silicon Cochlea Model -- 4.2.7 Adding the Active Nonlinear Behavior of the OHCs -- 4.3 Spike-Based Cochleas -- 4.3.1 Q-control of AEREAR2 Filters -- 4.3.2 Applications: Spike-Based Auditory Processing -- 4.4 Tree Diagram -- 4.5 Discussion -- References -- 5 Locomotion Motor Control -- 5.1 Introduction -- 5.1.1 Determining Functional Biological Elements -- 5.1.2 Rhythmic Motor Patterns -- 5.2 Modeling Neural Circuits in Locomotor Control -- 5.2.1 Describing Locomotor Behavior -- 5.2.2 Fictive Analysis -- 5.2.3 Connection Models -- 5.2.4 Basic CPG Construction -- 5.2.5 Neuromorphic Architectures -- 5.3 Neuromorphic CPGs at Work -- 5.3.1 A Neuroprosthesis: Control of Locomotion in Vivo -- 5.3.2 Walking Robots -- 5.3.3 Modeling Intersegmental Coordination -- 5.4 Discussion -- References -- 6 Learning in Neuromorphic Systems -- 6.1 Introduction: Synaptic Connections, Memory, and Learning -- 6.2 Retaining Memories in Neuromorphic Hardware -- 6.2.1 The Problem of Memory Maintenance: Intuition -- 6.2.2 The Problem of Memory Maintenance: Quantitative Analysis -- 6.2.3 Solving the Problem of Memory Maintenance -- 6.3 Storing Memories in Neuromorphic Hardware -- 6.3.1 Synaptic Models for Learning -- 6.3.2 Implementing a Synaptic Model in Neuromorphic Hardware -- 6.4 Toward Associative Memories in Neuromorphic Hardware -- 6.4.1 Memory Retrieval in Attractor Neural Networks -- 6.4.2 Issues -- 6.5 Attractor States in a Neuromorphic Chip -- 6.5.1 Memory Retrieval -- 6.5.2 Learning Visual Stimuli in Real Time -- 6.6 Discussion -- References -- Part II Building Neuromorphic Systems -- 7 Silicon Neurons -- 7.1 Introduction -- 7.2 Silicon Neuron Circuit Blocks.
7.2.1 Conductance Dynamics -- 7.2.2 Spike-Event Generation -- 7.2.3 Spiking Thresholds and Refractory Periods -- 7.2.4 Spike-Frequency Adaptation and Adaptive Thresholds -- 7.2.5 Axons and Dendritic Trees -- 7.2.6 Additional Useful Building Blocks -- 7.3 Silicon Neuron Implementations -- 7.3.1 Subthreshold Biophysically Realistic Models -- 7.3.2 Compact I&F Circuits for Event-Based Systems -- 7.3.3 Generalized I&F Neuron Circuits -- 7.3.4 Above Threshold, Accelerated-Time, and Switched-Capacitor Designs -- 7.4 Discussion -- References -- 8 Silicon Synapses -- 8.1 Introduction -- 8.2 Silicon Synapse Implementations -- 8.2.1 Non Conductance-Based Circuits -- 8.2.2 Conductance-Based Circuits -- 8.2.3 NMDA Synapse -- 8.3 Dynamic Plastic Synapses -- 8.3.1 Short-Term Plasticity -- 8.3.2 Long-Term Plasticity -- 8.4 Discussion -- References -- 9 Silicon Cochlea Building Blocks -- 9.1 Introduction -- 9.2 Voltage-Domain Second-Order Filter -- 9.2.1 Transconductance Amplifier -- 9.2.2 Second-Order Low-Pass Filter -- 9.2.3 Stability of the Filter -- 9.2.4 Stabilised Second-Order Low-Pass Filter -- 9.2.5 Differentiation -- 9.3 Current-Domain Second-Order Filter -- 9.3.1 The Translinear Loop -- 9.3.2 Second-Order Tau Cell Log-Domain Filter -- 9.4 Exponential Bias Generation -- 9.5 The Inner Hair Cell Model -- 9.6 Discussion -- References -- 10 Programmable and Configurable Analog Neuromorphic ICs -- 10.1 Introduction -- 10.2 Floating-Gate Circuit Basics -- 10.3 Floating-Gate Circuits Enabling Capacitive Circuits -- 10.4 Modifying Floating-Gate Charge -- 10.4.1 Electron Tunneling -- 10.4.2 pFET Hot-Electron Injection -- 10.5 Accurate Programming of Programmable Analog Devices -- 10.6 Scaling of Programmable Analog Approaches -- 10.7 Low-Power Analog Signal Processing -- 10.8 Low-Power Comparisons to Digital Approaches: Analog Computing in Memory.
10.9 Analog Programming at Digital Complexity: Large-Scale Field Programmable Analog Arrays -- 10.10 Applications of Complex Analog Signal Processing -- 10.10.1 Analog Transform Imagers -- 10.10.2 Adaptive Filters and Classifiers -- 10.11 Discussion -- References -- 11 Bias Generator Circuits -- 11.1 Introduction -- 11.2 Bias Generator Circuits -- 11.2.1 Bootstrapped Current Mirror Master Bias Current Reference -- 11.2.2 Master Bias Power Supply Rejection Ratio (PSRR) -- 11.2.3 Stability of the Master Bias -- 11.2.4 Master Bias Startup and Power Control -- 11.2.5 Current Splitters: Obtaining a Digitally Controlled Fraction of the Master Current -- 11.2.6 Achieving Fine Monotonic Resolution of Bias Currents -- 11.2.7 Using Coarse-Fine Range Selection -- 11.2.8 Shifted-Source Biasing for Small Currents -- 11.2.9 Buffering and Bypass Decoupling of Individual Biases -- 11.2.10 A General Purpose Bias Buffer Circuit -- 11.2.11 Protecting Bias Splitter Currents from Parasitic Photocurrents -- 11.3 Overall Bias Generator Architecture Including External Controller -- 11.4 Typical Characteristics -- 11.5 Design Kits -- 11.6 Discussion -- References -- 12 On-Chip AER Communication Circuits -- 12.1 Introduction -- 12.1.1 Communication Cycle -- 12.1.2 Speedup in Communication -- 12.2 AER Transmitter Blocks -- 12.2.1 AER Circuits within a Pixel -- 12.2.2 Arbiter -- 12.2.3 Other AER Blocks -- 12.2.4 Combined Operation -- 12.3 AER Receiver Blocks -- 12.3.1 Chip-Level Handshaking Block -- 12.3.2 Decoder -- 12.3.3 Handshaking Circuits in Receiver Pixel -- 12.3.4 Pulse Extender Circuits -- 12.3.5 Receiver Array Peripheral Handshaking Circuits -- 12.4 Discussion -- References -- 13 Hardware Infrastructure -- 13.1 Introduction -- 13.1.1 Monitoring AER Events -- 13.1.2 Sequencing AER Events -- 13.1.3 Mapping AER Events.
13.2 Hardware Infrastructure Boards for Small Systems -- 13.2.1 Silicon Cortex -- 13.2.2 Centralized Communication -- 13.2.3 Composable Architecture Solution -- 13.2.4 Daisy-Chain Architecture -- 13.2.5 Interfacing Boards using Serial AER -- 13.2.6 Reconfigurable Mesh-Grid Architecture -- 13.3 Medium-Scale Multichip Systems -- 13.3.1 Octopus Retina + IFAT -- 13.3.2 Multichip Orientation System -- 13.3.3 CAVIAR -- 13.4 FPGAs -- 13.5 Discussion -- References -- 14 Software Infrastructure -- 14.1 Introduction -- 14.1.1 Importance of Cross-Community Commonality -- 14.2 Chip and System Description Software -- 14.2.1 Extensible Markup Language -- 14.2.2 NeuroML -- 14.3 Configuration Software -- 14.4 Address Event Stream Handling Software -- 14.4.1 Field-Programmable Gate Arrays -- 14.4.2 Structure of AE Stream Handling Software -- 14.4.3 Bandwidth and Latency -- 14.4.4 Optimization -- 14.4.5 Application Programming Interface -- 14.4.6 Network Transport of AE Streams -- 14.5 Mapping Software -- 14.6 Software Examples -- 14.6.1 ChipDatabase - A System for Tuning Neuromorphic aVLSI Chips -- 14.6.2 Spike Toolbox -- 14.6.3 jAER -- 14.6.4 Python and PyNN -- 14.7 Discussion -- References -- 15 Algorithmic Processing of Event Streams -- 15.1 Introduction -- 15.2 Requirements for Software Infrastructure -- 15.2.1 Processing Latency -- 15.3 Embedded Implementations -- 15.4 Examples of Algorithms -- 15.4.1 Noise Reduction Filters -- 15.4.2 Time-Stamp Maps and Subsampling by Bit-Shifting Addresses -- 15.4.3 Event Labelers as Low-Level Feature Detectors -- 15.4.4 Visual Trackers -- 15.4.5 Event-Based Audio Processing -- 15.5 Discussion -- References -- 16 Towards Large-Scale Neuromorphic Systems -- 16.1 Introduction -- 16.2 Large-Scale System Examples -- 16.2.1 Spiking Neural Network Architecture -- 16.2.2 Hierarchical AER -- 16.2.3 Neurogrid.
16.2.4 High Input Count Analog Neural Network System.
Abstract:
Shih-Chii Liu is a group leader at the Institute of Neuroinformatics, University of Zurich and ETH Zurich. She received her Ph.D. in the Computation and Neural Systems program at Caltech. She has been an instructor and topic organizer at the NSF Telluride Neuromorphic Cognition Engineering Workshop in Telluride, Colorado since 1998. She has also co-authored a book on analog VLSI circuits (published by MIT Press), is an IEEE Senior member and has held offices in a number of scientific and IEEE engineering international conferences. Dr Liu has been working on event-based vision and auditory sensors, multi-neuron networks, and asynchronous circuits for more than 20 years. Tobi Delbruck has been Professor of Physics and Electrical Engineering at the Institute of Neuroinformatics since 1998. He leads the Sensors group which focuses on neuromorphic sensors and processing. He received his Ph.D. in the Computation and Neural Systems program at Caltech. He worked on electronic imaging at Arithmos, Synaptics, National Semiconductor, and Foveon. He co-organized the Telluride Neuromorphic Cognition Engineering summer workshop and the live demonstration sessions at ISCAS and NIPS, and is former chair of the IEEE CAS Sensory Systems Technical Committee. He has been awarded 9 IEEE awards and is an IEEE Fellow. Giacomo Indiveri is a Professor at the University of Zurich's Faculty of Science. He obtained his M.Sc. degree in Electrical Engineering and his Ph.D. degree in Computer Science from the University of Genoa, Italy. He is an ERC fellow and an IEEE Senior member. His research interests lie in the study of real and artificial neural processing systems, and in the hardware implementation of neuromorphic cognitive systems, using full custom analog and digital VLSI technology. Adrian M. Whatley gained a degree in Chemistry at the University of Bristol
in England in 1986. After working for 10 years in the British computer industry, he took up his current software engineering position at the Institute of Neuroinformatics where he works primarily on asynchronous Address-Event communication systems. Rodney Douglas is a co-founder of the Institute of Neuroinformatics. His central research interest over the past 25 years has been the nature of computation by the circuits of the neocortex and their implementation both in software simulation, in custom electronic hardware. The experimental aspect of his work has inspired a number of cortical models of processing that use recurrently connected neuronal architectures. He is currently exploring principles of self-assembly in simple organisms and circuits which he considers crucial for building truly autonomous neuromorphic cognitive systems.
Local Note:
Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2017. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries.
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