Cover -- Preface -- Acknowledgement -- Contents -- Chapter 1. Number Systems and Codes -- 1.0 Introduction -- 1.1 A Review of The Decimal System -- 1.2 Binary Numbering System -- 1.2.1 Binary to Decimal Conversion -- 1.2.2 Decimal to Binary Conversion -- 1.2.3 Binary Formats -- 1.2.4 Data Organization -- 1.3 Octal Numbering System -- 1.3.1 Octal to Decimal, Decimal to Octal Conversion -- 1.3.2 Octal to Binary, Binary to Octal Conversion -- 1.4 Hexadecimal Numbering System -- 1.4.1 Hex to Decimal and Decimal to Hex Conversion -- 1.4.2 Hex to Binary and Binary to Hex Conversion -- 1.4.3 Hex to Octal and Octal to Hex Conversion -- 1.5 Range to Number Representation -- 1.6 Binary Arithmetic -- 1.7 Negative Numbers and Their Arithmetic -- 1.7.1 1's and 2's Complement -- 1.7.2 Subtraction Using 1's and 2's Complement -- 1.7.3 Signed Binary Representation -- 1.7.4 Arithmetic Overflow -- 1.7.5 9's and 10's Complement -- 1.7.6 r's Complement and (r-1)'s Complement -- 1.7.7 Rules for Subtraction using (r-1)'s Complement -- 1.7.8 Rules for Subtraction using r's Complement -- 1.8 Binary Coded Decimal (BCD) and Its Arithmetic -- 1.9 Codes -- 1.9.1 Weighted Binary Codes -- 1.9.2 Non-Weighted Codes -- 1.9.3 Error Detecting Codes -- 1.9.4 Error Correcting Codes -- 1.9.5 Hamming Code -- 1.9.6 Cyclic Codes -- 1.9.7 Alphanumeric Codes -- 1.10 Solved Examples -- 1.11 Exercises -- Chapter 2. Digital Design Fundamentals Boolean Algebra and Logic Gates -- 2.0 Introductory Concepts of Digital Design -- 2.1 Truth Table -- 2.2 Axiomatic Systems and Boolean Algebra -- 2.2.1 Huntington's Postulates -- 2.2.2 Basic Theorems and Properties of Boolean Algebra -- 2.3 Boolean Functions -- 2.3.1 Transformation of Boolean Function into Logic Diagram -- 2.3.2 Complement of a Function -- 2.4 Representation of Boolean Functions -- 2.4.1 Minterm and Maxterm Realization.

2.4.2 Standard Forms -- 2.4.3 Conversion between Standard Forms -- 2.5 Logic Gates -- 2.5.1 Positive and Negative Logic Designation -- 2.5.2 Gate Definition -- 2.5.3 The AND Gate -- 2.5.4 The OR Gate -- 2.5.5 The Inverter and Buffer -- 2.5.6 Other Gates and Their Functions -- 2.5.7 Universal Gates -- 2.5.8 The Exclusive OR Gate -- 2.5.9 The Exclusive NOR gate -- 2.5.10 Extension to Multiple Inputs in Logic Gates -- 2.6 NAND and NOR Implementation -- 2.6.1 Implementation of a Multistage (or Multistage (or Multilevel) Digial Circuit using NAND Gates Only -- 2.6.2 Implementation of a Multilevel Digital Circuit using NOR Gates only -- 2.7 Exercise -- Chapter 3. Boolean Function Minimization Techniques -- 3.0 Introduction -- 3.1 Minimization Using Postulates and Theorem of Boolean Algebra -- 3.2 Minimization Using Karnaugh Map (K-Map) Method -- 3.2.1 Two and Three Variable K Map -- 3.2.2 Boolean Expression Minimization Using K-Map -- 3.2.3 Minimization in Products of Sums Form -- 3.2.4 Four Variable K-Map -- 3.2.5 Prime and Essential Implicants -- 3.2.6 Don't Care Map Entries -- 3.2.7 Five Variable K-Map -- 3.2.8 Six Variable K-Map -- 3.2.9 Multi Output Minimization -- 3.3 Minimization Using Quine-McCluskey (Tabular) Method -- 3.4 Exercise -- Chapter 4. Combinational Logic -- 4.0 Introduction -- 4.1 Arithmatic Circuits -- 4.1.1 Adders -- 4.1.2 Subtractors -- 4.1.3 Code Converters -- 4.1.4 Parity Generators and Checkers -- 4.2 MSI and LSI Circuits -- 4.2.1 The Digital Multiplexers -- 4.2.2 Decoders (Demultiplexers) -- 4.2.3 Encoders -- 4.2.4 Serial and Parallel Adders -- 4.2.5 Decimal Adder -- 4.2.6 Magnitude Comparator -- 4.3 Hazards -- 4.3.1 Hazards in Combinational Circuits -- 4.3.2 Types of Hazards -- 4.3.3 Hazard Free Realizations -- 4.3.4 Essential Hazard -- 4.3.5 Significance of Hazards -- 4.4 Exercise -- Chapter 5. Programmable Logic Devices.

5.0 Introduction -- 5.1 Read Only Memory (ROM) -- 5.1.1 Realizing Logical Functions with ROM -- 5.2 Programmable Logic Arrays -- 5.2.1 Realizing Logical Functions with PLAs -- 5.3 Programmable Arrary Logic (PAL) -- 5.3.1 Commercially Available SPLDs -- 5.3.2 Generic Array Logic (GAL) -- 5.3.3 Applications of PLDs -- 5.4 Complex Programmable Logic Devices (CPLD) -- 5.4.1 Applications of CPLDs -- 5.5 Field-Programmable Gate Arrays (FPGA) -- 5.5.1 Applications of FPGAs -- 5.6 User-Programmable Switch Technologies -- 5.7 Exercise -- Chapter 6. Synchronous (Clocked) Sequential Circuits -- 6.0 Introduction -- 6.1 Flip-Flops -- 6.1.1 RS Flip-Flop -- 6.1.2 Flip-Flop -- 6.1.3 Clocked Flip-Flops -- 6.1.4 Triggering of Flip-Flops -- 6.1.5 JK and T Flip-Flops -- 6.1.6 Race Around Condition and Solution -- 6.1.7 Operating Characteristics of Flip-Flops -- 6.1.8 Flip-Flop Applications -- 6.2 Flip-Flop Excitation Table -- 6.3 Flip-Flop Conversions -- 6.4 Analysis of Clocked Sequential Circuits -- 6.5 Design of Clocked Sequential Circuits -- 6.6 Design Examples -- 6.7 Solved Examples -- 6.8 Exercise -- Chapter 7. Shift Registers and Counters -- 7.0 Introduction -- 7.1 Shift Registers -- 7.2 Modes of Operations -- 7.2.1 Serial In-Serial Out Shift Registers -- 7.2.2 Serial In-Parallel Out Shift Registers -- 7.2.3 Parallel In-Serial Out Shift Registers -- 7.2.4 Parallel In-Parallel Out Shift Registers -- 7.2.5 Bidirectional Shift Registers (Universal Shift Register) -- 7.3 Applications of Shift Registers -- 7.3.1 To Produce Time Delay -- 7.3.2 Simplify Combinational Logic -- 7.3.3 To Convert Serial Data to Parallel Data -- 7.4 Counters -- 7.4.1 Introduction -- 7.4.2 Binary Ripple Up-Counter -- 7.4.3 4-Bit Binary Ripple Up-Counter -- 7.4.5 Up-Down Counters -- 7.4.6 Reset and Preset Functions -- 7.4.7 Universal Synchronous Counter Stage -- 7.4.8 Modulus Counters.

7.4.9 Asynchronous Counters (Counter Reset Method) -- 7.4.10 Logic Gating Method -- 7.4.11 Design of Synchronous Counters -- 7.4.12 Lockout -- 7.4.13 Ring Counter -- 7.4.14 Johnson Counter -- 7.4.15 Ring Counter Applications -- 7.5 Exercise -- Chapter 8. Introductory Concept of Finite State Machines -- 8.0 Introduction -- 8.1 General Model of FSM -- 8.2 Classification of FSM (Mealy & Moore Models) -- 8.3 Design of FSM -- 8.4 Design Examples -- 8.5 Capabilities and Limitations of Finite State Machines -- 8.6 Exercise -- Chpater 9. Asynchronous Sequential Logic -- 9.0 Introduction -- 9.1 Difference Between Synchronous and Asynchronous -- 9.2 Modes of Operation -- 9.3 Analysis of Asynchronous Sequential Machines -- 9.3.1 Fundamental Mode Circuits -- 9.3.2 Circuits without Latches -- 9.3.3 Transition Table -- 9.3.4 Flow Table -- 9.3.5 Circuits with Latches -- 9.3.6 Races and Cycles -- 9.3.7 Pulse-mode Circuits -- 9.4 Asynchronous Sequential Circuit Design -- 9.4.1 Design Steps -- 9.4.2 Reduction of States -- 9.4.3 Merger Diagram -- 9.5 Essential Hazards -- 9.6 Hazard-Free Realization Using S-R Flip-Flops -- 9.7 Solved Examples -- 9.8 Exercise -- Chapter 10. Threshold Logic -- 10.0 Introduction -- 10.1 The Threshold Element Or T Gate -- 10.2 Physical Realization of Threshold Gate -- 10.3 Capabilities of Threshold Gate -- 10.4 Properties of Threshold Functions -- 10.5 Synthesis of Threshold Functions -- 10.6 Multi-Gate Synthesis -- 10.7 Limitations of T-Gate -- 10.8 Exercise -- Chapter 11. Algorithmic State Machine -- 11.0 Introduction -- 11.1 Design of Digital System -- 11.2 The Elements and Structure of The ASM Chart -- 11.2.1 ASM Block -- 11.2.2 Register Operation -- 11.2.3 Example ASM Charts -- 11.3 ASM Timing Considerations -- 11.4 Data Processing Unit -- 11.5 Control Design -- 11.5.1 Multiplexer Control -- 11.5.2 PLA Control -- 11.6 Exercise.

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