Cover -- Half-Title -- Smart Embedded Systems andApplications -- RIVER PUBLISHERS SERIES IN ELECTRONIC MATERIALS, CIRCUITS AND DEVICES -- Title -- Copyrights -- Dedicate -- Contents -- Preface -- Acknowledgments -- List of Reviewers -- List of Figures -- List of Tables -- List of Notations and Abbreviations -- SECTION 1 Smart Embedded Systems for the Automotive Industry -- 1Functional Safety Audit/Assessment for Automotive Engineering -- Abstract -- 1.1 Introduction and Objectives -- 1.2 ISO 26262 and ASIL Overview -- 1.3 Functional Safety Audit/Assessment Program -- 1.3.1 Internal functional safety audit procedure -- 1.3.1.1 Definition and safety compliance procedures phases -- 1.3.1.2 Objective and scope of internal FS audit -- 1.3.1.3 Internal functional safety audit procedure: -- 1.3.1.4 Non-Conformance -- 1.3.2 Internal functional safety assessment procedure -- 1.3.2.1 Objective and scope of internal FS assessment -- 1.3.2.2 Project FSA procedure: -- 1.3.3 External or supplier functional safety audit and functional safety assessment -- 1.4 Functional Safety Audit / Assessment Planning -- 1.5 Functional Safety Audit / Assessment Preparation -- 1.6 Functional Safety Audit / Assessment Performance -- 1.7 Functional Safety Audit / Assessment Report and Follow-up -- 1.8 Conclusion -- References -- 2Comparison between AUTOSAR Platforms with Functional Safety for Automotive Software Architectures -- Abstract -- 2.1 Introduction -- 2.2 Overview of the Future E/E Architectures -- 2.2.1 Combination of different software platforms -- 2.2.2 Service oriented communication -- 2.3 The AUTOSAR Adaptive Platform -- 2.4 AUTOSAR Foundation -- 2.5 Classic AUTOSAR Vs Adaptive AUTOSAR -- 2.6 Communication Between AUTOSAR Platforms -- 2.7 Safety Preliminaries for E/E Architectures -- 2.7.1 Functional safety overview -- 2.7.2 ASIL determination -- 2.8 Conclusion.

References -- 3Hardware-in-the-Loop System for Electronic Control Unit Software and Calibration Development -- Abstract -- 3.1 Introduction -- 3.2 Automotive Embedded Systems Overview -- 3.2.1 Automotive systems -- 3.2.2 Electronic control units -- 3.2.3 Hardware-in-the-loop systems -- 3.3 HIL for Engine Calibration: A Case Study -- 3.3.1 System setup -- 3.3.2 Signal manipulation -- 3.3.3 Engine model -- 3.3.4 Overall system -- 3.4 Experimental Evaluation and Measurements -- 3.4.1 Experimental setup -- 3.4.2 Experiment measurements -- 3.4.3 Engine model accuracy results -- 3.4.4 Cam-Crank signal generator results -- 3.4.5 Open-loop performance -- 3.4.6 Closed-loop performance -- 3.5 Conclusion -- 3.6 Acknowledgements -- References -- SECTION 2 Utilizing Embedded Systems for UAVs -- 4 Processor in the Loop Experiments of an Adaptive Trajectory Tracking Control for Quadrotor UAVs -- Abstract -- 4.1 Introduction -- 4.2 Quadrotor Modeling -- 4.3 Controller Design -- 4.4 Processor-in-the-Loop Experiments -- 4.5 Conclusion -- References -- SECTION 3 Smart Embedded Systems in Biomedicine -- 5A Detailed Review on Embedded Based Heartbeat Monitoring Systems -- Abstract -- 5.1 Introduction -- 5.2 Measuring Methods -- 5.3 Categorisation of Algorithms for Heartbeat Detection -- 5.3.1 Categorisation of heartbeat displacement models -- 5.3.2 Demodulation techniques -- 5.4 Various Embedded Applications in the Medical Field -- 5.4.1 Software related to embedded systems -- 5.5 Embedded System Hardware for Heartbeat Monitoring -- 5.6 Conclusion -- References -- 6Embedded Systems in Biomedical Engineering: Case of ECG Signal Processing Using Multicores CPU and FPGA Architectures -- Abstract -- 6.1 Introduction -- 6.2 Embedded System Architectures -- 6.2.1 Embedded systems overview -- 6.2.2 Embedded systems architectures -- 6.2.2.1 Standalone architectures.

6.2.2.2 Heterogeneous architectures -- 6.3 Embedded Systems Applications in Biomedical Engineering: Case of the Pre-treatment of ECG Signal -- 6.3.1 The proposed techniques for embedded systems implementations -- 6.3.1.1 ADTF technique -- 6.3.1.2 DWT Technique -- 6.3.1.3 Hybrid DWT-ADTF technique -- 6.3.2 Implementation of the ADTF technique usingmulti-CPU architectures -- 6.3.3 HLS implementation of ADTF techniqueusing FPGA architecture -- 6.3.4 VHDL implementation of ADTF techniqueusing FPGA architecture -- 6.3.5 VHDL implementation of hybrid DWT-ADTF technique using FPGA architecture -- 6.4 Conclusions -- References -- 7Acquisition and Processing of SurfaceEMG Signal with an Embedded Compact RIO-based System -- Abstract -- 7.1 Introduction -- 7.2 EMG Signal Conditioning Circuit -- 7.2.1 Instrumentation amplifier -- 7.2.2 Band pass filter -- 7.2.3 Analog-to-digital converter -- 7.3 EMG Signal Processing -- 7.3.1 Flowchart description -- 7.4 Implementation Results -- 7.4.1 Implementation on compact RIO-9035 controller -- 7.4.2 EMG instrumentation based on NI-ELVIS II+ -- 7.4.3 Real-time evaluation -- 7.5 Conclusion -- 7.6 Funding -- 7.7 ORCID ID -- References -- SECTION 4 The Application of Embedded System in Image Processing -- 8Quick and Efficient Hardware-Software Design Space Exploration UsingVivado-HLS: A Case Study of Adaptive Algorithm for Image Denoising -- Abstract -- 8.1 Introduction -- 8.2 High-level Synthesis -- 8.3 Adaptive Algorithm -- 8.3.1 LMS algorithm -- 8.3.2 NLMS algorithm -- 8.4 Implementation and Results -- 8.4.1 Phase I -- 8.4.2 Phase II -- 8.4.3 Phase III -- 8.5 Conclusion and Future Scope -- References -- 9Fast FPGA Implementation of A Moving Object Detection System -- Abstract -- 9.1 Introduction -- 9.2 Detect Moving Objects Algorithm -- 9.3 Implementation and Experiment Results -- 9.3.1 Software simulation and evaluation.

9.3.2 Embedded objects detection system -- 9.4 Conclusion -- References -- 10Face Recognition based on CNN, Hog and Haar Cascade Methods using RaspberryPi v4 Model B -- Abstract -- 10.1 Introduction -- 10.2 Implementation Methods -- 10.2.1 Method 1. Haar cascade -- 10.2.2 Method 2. Histogram of Oriented Gradients (HOG) -- 10.2.3 Method 3. Convolutional Neural Networks (CNN) -- 10.2.3.1 Convolution layer -- 10.2.3.2 Pooling layer -- 10.2.3.3 Fully connected layer -- 10.3 Deployment Environments and Results -- 10.3.1 Hardware environment -- 10.3.1.1 Raspberry Pi4 -- 10.3.1.2 Camera Pi V2 -- 10.3.2 Software environment -- 10.3.2.1 Python -- 10.3.3 Application process/steps -- 10.3.3.1 Dataset creation -- 10.3.3.2 Training part -- 10.3.3.3 Recognition part -- 10.3.4 Implementation results and comparison -- 10.4 Conclusion -- References -- SECTION 5 Internet of Things BasedEmbedded System -- 11Survey Review on Artificial Intelligence and Embedded Systems for Agriculture Safety: A proposed IoT Agro-meteorology System for Local Farmers in Morocco -- Abstract -- 11.1 Introduction -- 11.2 AI-enabled Embedded Systems for Agriculture -- 11.2.1 Precision in water management -- 11.2.2 Integrated food safety -- 11.2.3 Crop productivity and fertility -- 11.2.4 Automation: Unmanned aerial vehicles (UAVs) and robots -- 11.2.5 Weather predictive analysis -- 11.3 Proposed Solution for Familial Agriculture andSmall Farmers -- 11.3.1 Description of the study area -- 11.3.2 Model architecture -- 11.3.3 Wireless sensors networks for agricultural Forecasting -- 11.3.4 Communication modules -- 11.4 Discussions: Questions and Challenges Raised by the use of AI and IoT in Agriculture -- 11.4.1 The question of trust -- 11.4.2 The question of applying AI stochastic algorithms -- 11.4.3 The question of data -- 11.4.4 The question of interpretability.

11.5 Conclusion and Future Works -- Appendix A -- Appendix B -- Appendix C -- Appendix D -- References -- 12IoT-Based Intelligent Handicraft System Using NFC Technology -- Abstract -- 12.1 Introduction -- 12.2 Preliminary and Related Work -- 12.3 System Design -- 12.3.1 Data acquisition -- 12.3.2 Data analysis -- 12.4 System Implementation -- 12.4.1 System workflow -- 12.4.2 Database design -- 12.4.3 Mobile application prototype -- 12.5 Conclusion -- 12.6 Acknowledgments -- References -- SECTION 6 System on Chip and Co-design -- 13SoC Power Estimation: A Short Review -- Abstract -- 13.1 Introduction -- 13.2 Background -- 13.2.1 Levels of parallelism -- 13.2.2 Advances in processor microarchitecture -- 13.2.2.1 Single cycle processor -- 13.2.2.2 Multi cycle processor -- 13.2.2.3 Pipelining -- 13.2.2.4 Superscalar processor -- 13.2.2.5 Vector processor -- 13.2.2.6 Multicore processors -- 13.2.3 Abstraction levels classification -- 13.2.3.1 Layout -- 13.2.3.2 Gate level -- 13.2.3.3 Register transfer level -- 13.2.3.4 Cycle accurate level -- 13.2.3.5 Transactional level modeling -- 13.2.3.6 Algorithmic level -- 13.3 Physical Power Models -- 13.3.1 Leakage power -- 13.3.2 Dynamic power -- 13.3.3 Short-circuit power -- 13.4 Power Estimation Techniques -- 13.4.1 WATTCH -- 13.4.2 AVALACHE -- 13.4.3 PowerVIP -- 13.4.4 Hybrid System Level power consumptionestimation (HSL) -- 13.4.5 Early Design Power Estimation (EDPE) -- 13.4.6 Recent power and temperature modelling method -- 13.5 Discussion -- 13.6 Proposed Technique -- 13.7 Conclusion -- References -- 14Hardware/Software Partitioning Algorithms: A Literature Review and New Perspectives -- Abstract -- 14.1 Introduction -- 14.2 Overview of Partitioning Problem -- 14.3 Exact Algorithms -- 14.3.1 Integer linear programming -- 14.3.2 Dynamic programming -- 14.3.3 Branch and bound.

14.4 Classical Heuristic Approaches.