Front Cover -- Reconfigurable Computing -- Copyright Page -- Table of Contents -- List of Contributors -- Preface -- Introduction -- Part I: Reconfigurable Computing Hardware -- Chapter 1. Device Architecture -- 1.1 Logic-The Computational Fabric -- 1.2 The Array and Interconnect -- 1.3 Extending Logic -- 1.4 Configuration -- 1.5 Case Studies -- 1.6 Summary -- References -- Chapter 2. Reconfigurable Computing Architectures -- 2.1 Reconfigurable Processing Fabric Architectures -- 2.2 RPF Integration into Traditional Computing Systems -- 2.3 Summary and Future Work -- References -- Chapter 3. Reconfigurable Computing Systems -- 3.1 Early Systems -- 3.2 PAM, VCC, and Splash -- 3.3 Small-Scale Reconfigurable Systems -- 3.4 Circuit Emulation -- 3.5 Accelerating Technology -- 3.6 Reconfigurable Supercomputing -- 3.7 Non-FPGA Research -- 3.8 Other System Issues -- 3.9 The Future of Reconfigurable Systems -- References -- Chapter 4. Reconfiguration Management -- 4.1 Reconfiguration -- 4.2 Configuration Architectures -- 4.3 Managing the Reconfiguration Process -- 4.4 Reducing Configuration Transfer Time -- 4.5 Configuration Security -- 4.6 Summary -- References -- Part II: Programming Reconfigurable Systems -- Chapter 5. Compute Models and System Architectures -- 5.1 Compute Models -- 5.2 System Architectures -- References -- Chapter 6. Programming FPGA Applications in VHDL -- 6.1 VHDL Programming -- 6.2 Hardware Compilation Flow -- 6.3 Limitations of VHDL -- References -- Chapter 7. Compiling C for Spatial Computing -- 7.1 Overview of How C Code Runs on Spatial Hardware -- 7.2 Automatic Compilation -- 7.3 Uses and Variations of C Compilation to Hardware -- 7.4 Summary -- References -- Chapter 8. Programming Streaming FPGA Applications Using Block Diagrams in Simulink -- 8.1 Designing High-Performance Datapaths Using Stream-Based Operators.

8.2 An Image-Processing Design Driver -- 8.3 Specifying Control in Simulink -- 8.4 Component Reuse: Libraries of Simple and Complex Subsystems -- 8.5 Summary -- References -- Chapter 9. Stream Computations Organized for Reconfigurable Execution -- 9.1 Programming -- 9.2 System Architecture and Execution Patterns -- 9.3 Compilation -- 9.4 Runtime -- 9.5 Highlights -- References -- Chapter 10. Programming Data Parallel FPGA Applications Using the SIMD/Vector Model -- 10.1 SIMD Computing on FPGAs: An Example -- 10.2 SIMD Processing Architectures -- 10.3 Data Parallel Languages -- 10.4 Reconfigurable Computers for SIMD/Vector Processing -- 10.5 Variations of SIMD/Vector Computing -- 10.6 Pipelined SIMD/Vector Processing -- 10.7 Summary -- References -- Chapter 11. Operating System Support for Reconfigurable Computing -- 11.1 History -- 11.2 Abstracted Hardware Resources -- 11.3 Flexible Binding -- 11.4 Scheduling -- 11.5 Communication -- 11.6 Synchronization -- 11.7 Protection -- 11.8 Summary -- References -- Chapter 12. The JHDL Design and Debug System -- 12.1 JHDL Background and Motivation -- 12.2 The JHDL Design Language -- 12.3 The JHDL CAD System -- 12.4 JHDL'S Hardware Mode -- 12.5 Advanced JHDL Capabilities -- 12.6 Summary -- References -- Part III: Mapping Designs to Reconfigurable Platforms -- Chapter 13. Technology Mapping -- 13.1 Structural Mapping Algorithms -- 13.2 Integrated Mapping Algorithms -- 13.3 Mapping Algorithms for Heterogeneous Resources -- 13.4 Summary -- References -- FPGA Placement -- Chapter 14. Placement for General-purpose FPGAs -- 14.1 The FPGA Placement Problem -- 14.2 Clustering -- 14.3 Simulated Annealing for Placement -- 14.4 Partition-Based Placement -- 14.5 Analytic Placement -- 14.6 Further Reading and Open Challenges -- References -- Chapter 15. Datapath Composition -- 15.1 Fundamentals -- 15.2 Tool Flow Overview.

15.3 The Impact of Device Architecture -- 15.4 The Interface to Module Generators -- 15.5 The Mapping -- 15.6 Placement -- 15.7 Compaction -- 15.8 Summary and Future Work -- References -- Chapter 16. Specifying Circuit Layout on FPGAs -- 16.1 The Problem -- 16.2 Explicit Cartesian Layout Specification -- 16.3 Algebraic Layout Specification -- 16.4 Layout Verification for Parameterized Designs -- 16.5 Summary -- References -- Chapter 17. PathFinder: A Negotiation-based, Performance-driven Router for FPGAs -- 17.1 The History of PathFinder -- 17.2 The PathFinder Algorithm -- 17.3 Enhancements and Extensions to PathFinder -- 17.4 Parallel PathFinder -- 17.5 Other Applications of the PathFinder Algorithm -- 17.6 Summary -- References -- Chapter 18. Retiming, Repipelining, and C-slow Retiming -- 18.1 Retiming: Concepts, Algorithm, and Restrictions -- 18.2 Repipelining and C-slow Retiming -- 18.3 Implementations of Retiming -- 18.4 Retiming on Fixed-Frequency FPGAs -- 18.5 C-slowing as Multi-Threading -- 18.6 Why Isn't Retiming Ubiquitous? -- References -- Chapter 19. Configuration Bitstream Generation -- 19.1 The Bitstream -- 19.2 Downloading Mechanisms -- 19.3 Software to Generate Configuration Data -- 19.4 Summary -- References -- Chapter 20. Fast Compilation Techniques -- 20.1 Accelerating Classical Techniques -- 20.2 Alternative Algorithms -- 20.3 Effect of Architecture -- 20.4 Summary -- References -- Part IV: Application Development -- Chapter 21. Implementing Applications with FPGAs -- 21.1 Strengths and Weaknesses of FPGAs -- 21.2 Application Characteristics and Performance -- 21.3 General Implementation Strategies for FPGA-based Systems -- 21.4 Implementing Arithmetic in FPGAs -- 21.5 Summary -- References -- Chapter 22. Instance-specific Design -- 22.1 Instance-specific Design -- 22.2 Partial Evaluation -- 22.3 Summary -- References.

Chapter 23. Precision Analysis for Fixed-point Computation -- 23.1 Fixed-point Number System -- 23.2 Peak Value Estimation -- 23.3 Wordlength Optimization -- 23.4 Summary -- References -- Chapter 24. Distributed Arithmetic -- 24.1 Theory -- 24.2 DA Implementation -- 24.3 Mapping DA onto FPGAs -- 24.4 Improving DA Performance -- 24.5 An Application of DA on an FPGA -- References -- Chapter 25. Cordic Architectures for FPGA Computing -- 25.1 Cordic Algorithm -- 25.2 Architectural Design -- 25.3 FPGA Implementation of Cordic Processors -- 25.4 Summary -- References -- Chapter 26. Hardware/Software Partitioning -- 26.1 The Trend Toward Automatic Partitioning -- 26.2 Partitioning of Sequential Programs -- 26.3 Partitioning of Parallel Programs -- 26.4 Summary and Directions -- References -- Part V: Case Studies of FPGA Applications -- Chapter 27. Spiht Image Compression -- 27.1 Background -- 27.2 Spiht Algorithm -- 27.3 Design Considerations and Modifications -- 27.4 Hardware Implementation -- 27.5 Design Results -- 27.6 Summary and Future Work -- References -- Chapter 28. Automatic Target Recognition Systems on Reconfigurable Devices -- 28.1 Automatic Target Recognition Algorithms -- 28.2 Dynamically Reconfigurable Designs -- 28.3 Reconfigurable Static Design -- 28.4 ATR Implementations -- 28.5 Summary -- References -- Chapter 29. Boolean Satisfiability: Creating Solvers Optimized for Specific Problem Instances -- 29.1 Boolean Satisfiability Basics -- 29.2 Sat-solving Algorithms -- 29.3 A Reconfigurable SAT Solver Generated According to an SAT Instance -- 29.4 A Different Approach to Reduce Compilation Time and Improve Algorithm Efficiency -- 29.5 Discussion -- References -- Chapter 30. Multi-FPGA Systems: Logic Emulation -- 30.1 Background -- 30.2 Uses of Logic Emulation Systems -- 30.3 Types of Logic Emulation Systems.

30.4 Issues Related to Contemporary Logic Emulation -- 30.5 The Need for Fast FPGA Mapping -- 30.6 Case Study: The Virtualogic VLE Emulation System -- 30.7 Future Trends -- 30.8 Summary -- References -- Chapter 31. The Implications of Floating Point for FPGAs -- 31.1 Why is Floating Point Difficult? -- 31.2 Floating-point Application Case Studies -- 31.3 Summary -- References -- Chapter 32. Finite Difference Time Domain: A Case Study Using FPGAs -- 32.1 The FDTD Method -- 32.2 FDTD Hardware Design Case Study -- 32.3 Summary -- References -- Chapter 33. Evolvable FPGAs -- 33.1 The Poe Model of Bioinspired Design Methodologies -- 33.2 Artificial Evolution -- 33.3 Evolvable Hardware -- 33.4 Evolvable Hardware: A Taxonomy -- 33.5 Evolvable Hardware Digital Platforms -- 33.6 Conclusions and Future Directions -- References -- Chapter 34. Network Packet Processing in Reconfigurable Hardware -- 34.1 Networking with Reconfigurable Hardware -- 34.2 Network Protocol Processing -- 34.3 Intrusion Detection and Prevention -- 34.4 Semantic Processing -- 34.5 Complete Networking System Issues -- 34.6 Summary -- References -- Chapter 35. Active Pages:Memory-centric Computation -- 35.1 Active Pages -- 35.2 Performance Results -- 35.3 Algorithmic Complexity -- 35.4 Exploring Parallelism -- 35.5 Defect Tolerance -- 35.6 Related Work -- 35.7 Summary -- References -- Part VI: Theoretical Underpinnings and Future Directions -- Chapter 36. Theoretical Underpinnings -- 36.1 General Computational Array Model -- 36.2 Implications of the General Model -- 36.3 Induced Architectural Models -- 36.4 Modeling Architectural Space -- 36.5 Implications -- References -- Chapter 37. Defect and Fault Tolerance -- 37.1 Defects and Faults -- 37.2 Defect Tolerance -- 37.3 Transient Fault Tolerance -- 37.4 Lifetime Defects -- 37.5 Configuration Upsets -- 37.6 Outlook -- References.

Chapter 38. Reconfigurable Computing and Nanoscale Architecture.