Contents -- Preface -- 1. Introduction -- 1.1 Single-Electron Effects -- 1.2 Early Observations of Single-Electron Effects -- 1.3 Basic Single-Electron Devices -- 1.3.1 Single-electron transistor. -- 1.3.2 Single-electron box -- 1.3.3 Multiple-tunnel junction -- 1.4 Scope of This Book -- 1.4.1 Introduction to subsequent chapters -- 2. Single-Electron Charging Effects -- 2.1 Introduction -- 2.2 Single Tunnel Junction -- 2.3 The Single-Electron Box. -- 2.3.1 The 'critical charge'. -- 2.3.2 Electrostatic energy changes -- 2.3.3 Energy diagram for the single-electron box. -- 2.4 The Single-Electron Transistor -- 2.4.1 Electrostatic energy changes -- 2.4.2 Tunnelling rates. -- 2.4.3 Offset charge -- 2.4.4 Calculation of I-V characteristics. -- 2.4.5 The Coulomb staircase -- 2.4.6 Energy band diagrams -- 2.5 Quantum Dots -- 2.5.1 Coulomb oscillations in quantum dots. -- 2.6 The Multiple-Tunnel Junction -- 3. Single-Electron Transistors in Silicon -- 3.1 Early Observations -- 3.2 SETs in Crystalline Silicon -- 3.2.1 SETs with lithographically defined islands -- 3.2.1.1 Etched islands. -- 3.2.1.2 Pattern-dependant oxidation -- 3.2.2 SETs using MOSFET structures -- 3.2.3 Crystalline silicon nanowire SETs -- 3.2.4 Room temperature Coulomb oscillations with large peak-to- valley ratio -- 3.2.5 Fabrication and characterization of nanowire SETs -- 3.2.5.1 Fabrication -- 3.2.5.2 Electrical characterization -- 3.3 Single-Electron Transistors in Nanocrystalline Silicon -- 3.3.1 Conduction in continuous nanocrystalline silicon films -- 3.3.2 Nanocrystalline silicon nanowire SETs -- 3.3.3 Point-contact nc-Si SET: Room temperature operation. -- 3.3.4 'Grain-boundary' engineering -- 3.3.5 SETs using discrete silicon nanocrystals -- 3.3.6 Comparison with crystalline silicon SETs. -- 3.3.7 Electron coupling effects in nanocrystalline silicon.

3.3.7.1 Electrostatic coupling effects -- 3.3.7.2 Electron wavefunction coupling effects. -- 3.4 Single-Electron Effects in Grown Si Nanowires and Nanochains. -- 4. Single-Electron Memory -- 4.1 Introduction -- 4.1.1 Multiple-tunnel junction memory. -- 4.2 MTJ Memories in Silicon. -- 4.2.1 The single-electron detector. -- 4.3 Single- and Few-Electron Memories with Floating Gates -- 4.4 Large-scale Integrated Single-Electron Memory in Nanocrystalline Silicon -- 4.5 Few-Electron Memory with Integrated SET/MOSFET -- 4.5.1 Silicon nanowire SETs for L-SEM application -- 4.5.1.1 Nanowire SET in crystalline silicon. -- 4.5.1.2 Nanowire SET in polycrystalline silicon -- 4.5.1.3 Potential for mass fabrication -- 4.5.2 Single-gate L-SEM -- 4.5.2.1 Single-gate L-SEM fabrication and characterization -- 4.5.3 Split-gate L-SEM -- 4.5.4 L-SEM 3 × 3 cell array. -- 4.5.4.1 Memory cell selection -- 4.5.4.2 Temperature dependence of memory cell characteristics -- 5. Few-Electron Transfer Devices -- 5.1 Introduction -- 5.2 Single-Electron Turnstiles and Pumps -- 5.2.1 Single-electron turnstile -- 5.2.2 Single-electron pump -- 5.2.3 Single-electron pump and turnstile using a semiconductor quantum dot -- 5.3 Few-Electron Devices using MTJs. -- 5.3.1 Operation of single r.f. signal MTJ electron pump. -- 5.3.2 Single r.f. signal MTJ electron pumps in GaAs -- 5.3.3 Single r.f. signal MTJ electron pumps in silicon -- 5.3.3.1 Device fabrication and experimental Characteristics -- 5.3.4 MTJ electron pump with multi-phase r.f. signals. -- 5.4 Single-Electron Transfer Devices in Silicon -- 5.4.1 Single-electron transfer using a CCD -- 5.4.2 SET/MOSFET single-electron pump and turnstile -- 5.5 Metrological Applications -- 6. Single-Electron Logic Circuits -- 6.1 Introduction -- 6.2 Voltage State Logic -- 6.2.1 SET inverter with resistive load -- 6.2.2 Complementary SET inverter.

6.2.3 Complementary SET NAND and NOR gates -- 6.2.4 Programmable SET logic -- 6.2.5 Logic using SETs with multiple input terminals -- 6.2.6 Effect of offset charge -- 6.3 Charge State Logic -- 6.3.1 Binary decision diagram logic -- 6.3.1.1 Binary decision diagram logic: Basic logic gates -- 6.3.1.2 Implementation of BDD logic circuits in GaAs. -- 6.3.2 Implementation of BDD logic circuits in silicon. -- 6.3.2.1 Two-way BDD switch using silicon nanowire SETs. -- 6.3.2.2 Extension to a 'universal' three-way switch -- 6.4 Quantum Cellular Automaton Circuits. -- 6.5 Single-Electron Parametron -- Bibliography -- Index.