Cover image for Defects in High-k Gate Dielectric Stacks Nano-Electronic Semiconductor Devices
Defects in High-k Gate Dielectric Stacks Nano-Electronic Semiconductor Devices
Title:
Defects in High-k Gate Dielectric Stacks Nano-Electronic Semiconductor Devices
Author:
Gusev, Evgeni. editor.
ISBN:
9781402043673
Physical Description:
XI, 492 p. online resource.
Series:
NATO Science Series II: Mathematics, Physics and Chemistry, 220
Contents:
PVD-HIGH-K GATE DIELECTRICS WITH FUSI GATE AND INFLUENCE OF PDA TREATMENT ON ON-STATE DRIVE CURRENT -- EXTREMELY HIGH-DENSITY CAPACITORS WITH ALD HIGH-K DIELECTRIC LAYERS -- TOWARDS UNDERSTANDING OF PROCESSINGNANOSTRUCTURE- PROPERTY INTER-RELATIONSHIPS IN HIGHK/METAL GATE STACKS -- ON THE CHARACTERIZATION OF ELECTRONICALLY ACTIVE DEFECTS IN HIGH-? GATE DIELECTRICS -- INELASTIC ELECTRON TUNNELLING SPECTROSCOPY (IETS) STUDY OF HIGH-K DIELECTRICS -- CHARACTERIZATION AND MODELING OF DEFECTS IN HIGH-K MEASUREMENTS LAYERS THROUGH FAST ELECTRICAL TRANSIENT -- CHARACTERIZATION OF ELECTRICALLY ACTIVE DEFECTS IN HIGH-K GATE DIELECTRICS USING CHARGE PUMPING -- IMPACT OF HIGH-? PROPERTIES ON MOSFET ELECTRICAL CHARACTERISTICS -- STRUCTURAL EVOLUTION AND POINT DEFECTS IN METAL OXIDE-BASED HIGH-? GATE DIELECTRICS -- DISORDERED STRUCTURE AND DENSITY OF GAP STATES IN HIGH-PERMITTIVITY THIN SOLID FILMS -- INTERDIFFUSION STUDIES OF HIGH-K GATE DIELECTRIC STACK CONSTITUENTS -- XPS/LEIS STUDY OF HIGH-K RARE EARTH (LU, YB) OXIDES AND SILICATES ON SI: THE EFFECT OF ANNEALING ON MICROSTRUCTURE EVOLUTION -- TRANSIENT CHARGING EFFECTS AND ITS IMPLICATIONS TO THE RELIABILITY OF HIGH-K DIELECTRICS -- DEFECT ENERGY LEVELS IN HIGH-K GATE OXIDES -- DEFECT-RELATED ISSUES IN HIGH-K DIELECTRICS -- STUDYING THE EFFECTS OF NITROGEN AND HAFNIUM INCORPORATION INTO THE SIO2/SI(100) INTERFACE WITH REPLICA-EXCHANGE MOLECULAR DYNAMICS AND DENSITYFUNCTIONAL- THEORY CALCULATIONS -- PROBING POINT DEFECTS AND TRAPS IN STACKS OF ULTRATHIN HAFNIUM OXIDES ON (100)SI BY ELECTRON SPIN RESONANCE: INTERFACES AND N INCORPORATION -- MECHANISM OF CHARGE TRAPPING REDUCTION IN SCALED HIGH-? GATE STACKS -- ELECTRICALLY ACTIVE INTERFACE AND BULK SEMICONDUCTOR DEFECTS IN HIGH-K / GERMANIUM STRUCTURES -- DEFECT AND COMPOSITION ANALYSIS OF AS-DEPOSITED AND NITRIDED (100)SI / SIO2/ HF1-XSIXO2 STACKS BY ELECTRON PARAMAGNETIC RESONANCE AND ION BEAM ANALYSIS -- DEFECTS AT THE HIGH-? /SEMICONDUCTOR INTERFACES INVESTIGATED BY SPIN DEPENDENT SPECTROSCOPIES -- FIXED OXIDE CHARGE IN Ru-BASED CHEMICAL VAPOUR DEPOSITED HIGH-? GATE STACKS -- ELECTRICAL DEFECTS IN ATOMIC LAYER DEPOSITED HFO2 FILMS ON SILICON: INFLUENCE OF PRECURSOR CHEMISTRIES AND SUBSTRATE TREATMENT -- THE EFFECTS OF RADIATION AND CHARGE TRAPPING ON THE RELIABILITY OF ALTERNATIVE GATE DIELECTRICS -- CAN LEIS SPECTRA CONTAIN INFORMATION ON SURFACE ELECTRONIC STRUCTURE OF HIGH-K DIELECTRICS? -- LOW SUBSTRATE DAMAGE HIGH-K REMOVAL AFTER GATE PATTERNING -- MONITORING OF FERMI LEVEL VARIATIONS AT METAL/HIGH-K INTERFACES WITH IN SITU X-RAY PHOTOELECTRON SPECTROSCOPY -- STRUCTURE, COMPOSITION AND ORDER AT INTERFACES OF CRYSTALLINE OXIDES AND OTHER HIGH-K MATERIALS ON SILICON -- INTERFACE FORMATION DURING EPITAXIAL GROWTH OF BINARY METAL OXIDES ON SILICON -- EFFECT OF CHEMICAL ENVIRONMENT AND STRAIN ON OXYGEN VACANCY FORMATION ENERGIES AT SILICONSILICON OXIDE INTERFACES -- DIELECTRIC AND INFRARED PROPERTIES OF ULTRATHIN SiO2 LAYERS ON Si(100) -- THE (1 0 0) SURFACE OF SEMICONDUCTOR SILICON (IN PASSIVATION PRACTICAL CONDITIONS): PREPARATION, EVOLUTION, -- CORRELATION BETWEEN DEFECTS, LEAKAGE CURRENTS AND CONDUCTION MECHANISMS IN THIN HIGH-K DIELECTRIC LAYERS -- ELECTRONIC STRUCTURE OF ZRO2 AND HFO2 -- HIGH-K GATE STACKS ELECTRICAL CHARACTERIZATION AT THE NANOSCALE USING CONDUCTIVE-AFM -- MAGNETIC DEFECTS IN PRISTINE AND HYDROGENTERMINATED NANODIAMONDS -- ON THE IMPORTANCE OF ATOMIC PACKING IN DETERMINING DIELECTRIC PERMITTIVITIES -- INVESTIGATION OF THE ELECTRONIC PROPERTIES OF THIN DIELECTRIC FILMS BY SCANNING PROBE MICROSCOPY.
Abstract:
The goal of this NATO Advanced Research Workshop (ARW) entitled “Defects in Advanced High-k Dielectric Nano-electronic Semiconductor Devices”, which was held in St. Petersburg, Russia, from July 11 to 14, 2005, was to examine the very complex scientific issues that pertain to the use of advanced high dielectric constant (high-k) materials in next generation semiconductor devices. The special feature of this workshop was focus on an important issue of defects in this novel class of materials. One of the key obstacles to high-k integration into Si nano-technology are the electronic defects in high-k materials. It has been established that defects do exist in high-k dielectrics and they play an important role in device operation. However, very little is known about the nature of the defects or about possible techniques to eliminate, or at least minimize them. Given the absence of a feasible alternative in the near future, well-focused scientific research and aggressive development programs on high-k gate dielectrics and related devices must continue for semiconductor electronics to remain a competitive income producing force in the global market.
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