Cover image for Dynamic reconfigurable network-on-chip design innovations for computational processing and communication
Dynamic reconfigurable network-on-chip design innovations for computational processing and communication
Title:
Dynamic reconfigurable network-on-chip design innovations for computational processing and communication
Author:
Hsiung, Pao-Ann.
ISBN:
9781615208081
Publication Information:
Hershey, Pa. : IGI Global (701 E. Chocolate Avenue, Hershey, Pennsylvania, 17033, USA), c2010.
Physical Description:
electronic texts (329 p. : ill.) : digital files.
Contents:
A NoC-Based Infrastructure to Enable Dynamic Self Reconfigurable Systems / Leandro Möller ... [et al.] -- Dynamically Reconfigurable Networks-on-Chip Using Runtime Adaptive Routers / Mário Véstias, Horácio Neto -- Keys for Administration of Reconfigurable NoC / Rachid Dafali, Jean-Philippe Diguet -- An Efficient Hardware/Software Communication Mechanism for Reconfigurable NoC / Wei-Wen Lin, Jih-Sheng Shen, Pao-Ann Hsiung -- Design Methodologies and Mapping Algorithms for Reconfigurable NoC-Based Systems / Vincenzo Rana, Marco Santambrogio, Alessandro Meroni -- From MARTE to Reconfigurable NoCs / Imran Quadri ... [et al.] -- Dynamic Reconfigurable NoCs / Vincenzo Rana, Marco Santambrogio, Simone Corbetta -- High-Level Programming of Dynamically Reconfigurable NoC-Based Heterogeneous Multicore SoCs / Wim Vanderbauwhede -- Dynamic Reconfigurable NoC (DRNoC) Architecture / Yana Krasteva, Eduardo de la Torre, Teresa Riesgo -- Dynamically Reconfigurable NoC for Future Heterogeneous Multi-core Architectures / Balal Ahmad, Ali Ahmadinia, Tughrul Arslan -- Reliability Aware Performance and Power Optimization in DVFS-Based On-Chip Networks / Aditya Yanamandra ... [et al.] -- SpaceWire Inspired Network-on-Chip Approach for Fault Tolerant System-on-Chip Designs / Björn Osterloh, Harald Michalik, Björn Fiethe -- A High-Performance and Low-Power On-Chip Network with Reconfigurable Topology / Mehdi Modarressi, Hamid Sarbazi-Azad.
Abstract:
Reconfigurable computing brings immense flexibility to on-chip processing while network-on-chip has improved flexibility in on-chip communication. Integrating these two areas of research reaps the benefits of both and represents the promising future of multiprocessor systems-on-chip. This book is the one of the first compilations written to demonstrate this future for network-on-chip design. Through dynamic and creative research into questions ranging from integrating reconfigurable computing techniques, to task assigning, scheduling and arrival, to designing an operating system to take advantage of the computing and communication flexibilities brought about by run-time reconfiguration and network-on-chip, it represents a complete source of the techniques and applications for reconfigurable network-on-chip necessary for understanding of future of this field.
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