Effect of Power Optimizations on Soft Error Rate -- Dynamic Models for Substrate Coupling in Mixed-Mode Systems -- Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs -- Automated Conversion of SystemC Fixed-Point Data Types -- Exploration of Sequential Depth by Evolutionary Algorithms -- Validation of Asynchronous Circuit Specifications Using IF/CADP -- On-Chip Property Verification Using Assertion Processors -- Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems -- A Switched Opamp Based 10 Bits Integrated ADC for Ultra Low Power Applications -- Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans -- Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures -- Optimizing SOC Test Resources Using Dual Sequences -- A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits -- Low Power Java Processor for Embedded Applications -- Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes -- Evaluation Methodology for Single Electron Encoded Threshold Logic Gates -- Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath -- Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths -- Stuck-At-Fault Testability of SPP Three-Level Logic Forms.