Contents -- Prologue -- Preface -- 1 Fundamentals of Timing Simulation -- 1.1 Introduction -- 1.2 Circuit Simulation -- 1.3 Transistor-Level Simulation -- 1.3.1 Switch-level simulation -- 1.3.2 Advanced transistor-level simulators -- 1.4 Timing Gate Level Simulation -- 1.4.1 Delay models at gate level -- 1.4.1.1 Zero and unit delay models -- 1.4.1.2 Static delay models -- 1.4.1.3 Dynamics effects -- 1.4.2 The event-driven simulation technique -- 1.5 Summary and Tendencies -- 2 Delay Models: Evolution and Trends -- 2.1 Introduction -- 2.1.1 Deterministic delay models -- 2.1.2 Non-deterministic delay models -- 2.2 Deterministic Delay Model Types -- 2.2.1 Zero and unitary delay models -- 2.2.2 Assignable delay models -- 2.2.2.1 Static delay models -- 2.2.2.2 Example of static delay model parameter characterization -- 2.2.2.3 Dynamic delay models -- 2.3 State of the Art in Delay Models -- 2.3.1 Classification of the proposed delay models -- 2.3.2 Delay model performance -- 2.3.3 Evolution and trends in delay models -- 3 Degradation and Inertial Effects -- 3.1 Introduction -- 3.1.1 Degradation and inertial effects -- 3.2 Degradation Delay Model -- 3.2.1 Behaviour regions -- 3.2.2 Degradation modelling -- 3.2.3 Physical interpretation of the degradation parameters -- 3.2.4 Limits between behaviour regions -- 3.2.4.1 Limit between the normal propagation region and the degradation region -- 3.2.4.2 Limit between the filtering region and the degradation region -- 3.3 The Importance of the Degradation Effect -- 3.3.1 Maximum device operation frequency -- 3.3.2 Comparison with classical calculations and results -- 3.4 Inertial Effect -- 3.4.1 Inertial delay model failure -- 3.4.2 Inertial effect algorithm -- 3.4.3 Results -- 4 CMOS Inverter Degradation Delay Model -- 4.1 Introduction -- 4.2 Technological Parameters -- 4.3 Normal Propagation Delay.

4.3.1 CMOS inverter transient response: regions of operation -- 4.3.1.1 Region I: overshoot -- 4.3.1.2 Region II: short-circuit -- 4.3.1.3 Region III: discharge -- 4.3.2 Actual response of the CMOS inverter -- 4.3.2.1 Step input response of the CMOS inverter -- 4.3.2.2 Limits between slow and fast input transitions -- 4.3.2.3 Critical transition time calculation -- 4.3.2.4 Delay calculation for fast input transitions -- 4.3.2.5 Delay calculation for slow input transitions -- 4.3.3 Output transition time calculation -- 4.4 Input-to-Output Coupling Capacitance Modelling -- 4.4.1 IOCC calculation for micron MOSFET's -- 4.4.2 IOCC calculation for submicron MOSFET's -- 4.4.2.1 Reduced IOCC estimation from SPICE model card -- 4.4.3 Comparison of IOCC models -- 4.4.4 IOCC modelling impact in the Inverter's timing characteristics -- 4.5 Modelling the Degradation Parameters -- 4.5.1 Modelling the first degradation parameter -- 4.5.2 Modelling the second degradation parameter -- 4.5.3 Ranges of interest for the external and internal parameters of the CMOS inverter -- 4.6 Obtaining the Value of Technological Parameters -- 4.6.1 Verification of the model for the first degradation parameter -- 4.6.2 Verification of the model for the second degradation parameter -- 4.7 Discussion -- 5 Gate-Level DDM -- 5.1 Introduction -- 5.2 DDM for Multi-Input Gates -- 5.2.1 Gate-level delay equations -- 5.2.1.1 Normal propagation delay -- 5.2.1.2 Degradation parameters -- 5.2.2 Gate-level degradation parameter multiplicity in multi-input gates -- 5.2.3 Exhaustive gate-level degradation model -- 5.3 Degradation Parameter Characterization Process -- 5.3.1 General degradation model validation -- 5.3.2 Gate-level degradation parameters extraction -- 5.3.2.1 Variation with the output load -- 5.3.2.2 Variation with the input transition time.

5.3.3 Characterization process complexity -- 5.4 Analysis of Results -- 5.4.1 Characterization results -- 5.4.2 Simplified model -- 5.5 Simplified Model Equations -- 5.6 Simplified Model Characterization Process -- 5.6.1 Basic model -- 5.6.1.1 Basic model equations -- 5.6.1.2 Basic model characterization process -- 5.6.2 Error estimation for the propagation delay -- 5.6.2.1 Expressions for error propagation -- 5.6.2.2 Example of error propagation towards the propagation delay -- 5.7 Discussion of Results -- 5.8 Appendix: Calculation of Error Sensitivity in the Propagation Delay With Respect to the Degradation Parameter Error -- 5.8.1 Sensitivity of the propagation delay with respect to parameter -- 5.8.2 Sensitivity of the propagation delay with respect to To -- 5.8.3 Sensitivity of parameter z with respect to A -- 5.8.4 Sensitivity of parameter z with respect to B -- 5.8.5 Sensitivity of To with respect to C -- 6 Logic Level Simulator Design and Implementation -- 6.1 Introduction -- 6.2 Object Oriented Methodologies: UML -- 6.2.1 UML introduction -- 6.2.2 UML representation -- 6.3 Global Analysis of HALOTIS -- 6.4 Analysis of Requirements -- 6.5 HALOTIS Design and Modelling -- 6.5.1 HALOTIS use case diagrams -- 6.5.2 Object models -- 6.6 HALOTIS Implementation -- 6.6.1 Implementation language and platform -- 6.6.2 Intermediate formats -- 6.6.3 Simulation core -- 6.6.4 HALOTIS tools -- 7 DDM Simulation Results -- 7.1 Introduction -- 7.2 Pulse Propagation -- 7.2.1 Isolated pulse -- 7.2.2 Train of equidistant pulses -- 7.3 Ring Oscillator Frequency -- 7.3.1 Simple oscillator -- 7.3.2 Oscillator with out-buffer -- 7.4 Metastable Behaviour -- 7.4.1 Simulation results -- 8 Accurate Measurement of the Switching Activity -- 8.1 Introduction -- 8.2 Selection of the Testing Environment -- 8.3 Measurement of the Switching Activity Based on DFWII.

8.4 Measurement of the Switching Activity Based on HSPICE -- 8.5 Comparison between DFWII versus HSPICE Measurements -- 8.6 Accurate Measurement of the Switching Activity: A HALOTIS Application -- 8.7 Conclusions -- References -- Index.