Design and Test of Digital Circuits byQuantum-Dot Cellular Automata -- Contents -- Preface -- Chapter 1 Introduction 1 -- 1.1 CHALLENGES -- 1.2 PREVIOUS WORK -- 1.3 CONTRIBUTIONS -- 1.4 BOOK OUTLINE -- References -- Chapter 2 Nano Devices and Architectures Overview 11 -- 2.1 NANOELECTRONIC DEVICES -- 2.1 NANOELECTRONIC DEVICES -- 2.2 NANO-SCALE CROSSBARS -- 2.3 ARCHITECTURES -- References -- Chapter 3 QCA 37 -- 3.1 QCA IMPLEMENTATION -- 3.2 CLOCKING -- 3.3 MOLECULAR ATTACHMENT -- 3.4 POWER GAIN AND DISSIPATION -- 3.5 QCA SIMULATORS -- 3.6 QCA CIRCUITS -- 3.7 COMPARISON OF NANOTECHNOLOGY DEVICES -- References -- Chapter 4 QCA Combinational Logic Design 69 -- 4.1 GATE-BASED COMBINATIONAL LOGIC DESIGN -- 4.2 LOGIC SYNTHESIS -- 4.3 STRUCTURAL DESIGN -- 4.4 AND-OR-INVERTER (AOI) GATE -- References -- Chapter 5 Logic-Level Testing and Defect Characterization 91 -- 5.1 LOGIC-LEVEL TESTING -- 5.2 DEFECT CHARACTERIZATION OF DEVICES -- References -- Chapter 6 Two-Dimensional Schemes for Clocking/Timing of QCA Circuits 143 -- 6.1 CLOCKING ANALYSIS -- 6.2 TWO-DIMENSIONAL QCA CLOCKING -- 6.3 TWO-DIMENSIONAL WAVE QCA CLOCKING -- 6.4 EXAMPLES OF QCA CIRCUITS -- 6.5 FEEDBACK PATHS -- 6.6 SIMULATION RESULTS -- 6.7 CONCLUSION -- References -- Chapter 7 Tile-Based QCA Design 171 -- 7.1 QCA DESIGN BY TILING -- 7.2 FULLY POPULATED GRID ANALYSIS -- 7.3 TILES BASED ON 3 × 3 GRIDS -- 7.4 ANALYSIS OF RESULTS -- 7.5 LOGIC ANALYSIS -- 7.6 EXAMPLES OF QCA CIRCUITS -- 7.7 CONCLUSION -- References -- Chapter 8 Sequential Circuit Design in QCA 213 -- 8.1 RS FLIP-FLOP AND D FLIP-FLOP IN QCA -- 8.2 TIMING CONSTRAINTS IN QCA SEQUENTIAL DESIGNThe -- 8.3 ALGORITHM FOR CLOCKING ZONE ASSIGNMENT -- 8.4 DEFECT CHARACTERIZATION OF QCA SEQUENTIAL CIRCUITS -- 8.5 DISCUSSION AND CONCLUSION -- References -- Chapter 9 QCA Memory 247 -- 9.1 INTRODUCTION -- 9.2 REVIEW OF QCA MEMORIES.

9.3 PARALLEL MEMORY ARCHITECTURE -- 9.4 SERIAL MEMORY ARCHITECTURE -- References -- Chapter 10 Implementing Universal Logic in QCA 287 -- 10.1 UNIVERSAL GATE -- 10.2 UNIVERSAL GATE DESIGNS -- 10.3 MEMORY-BASED LUT -- 10.4 MULTIPLEXER-BASED LUT -- 10.5 DISCUSSION AND CONCLUSION -- References -- Chapter 11 QCA Model for Computing and Energy Analysis 305 -- 11.1 REVIEW ON REVERSIBLE COMPUTING -- 11.2 MECHANICAL MODEL -- 11.3 ENTROPY AND DISSIPATION ANALYSIS -- 11.4 LANDAUER AND BENNETT CLOCKING SCHEMES -- 11.5 CONCLUSION -- References -- Chapter 12 Fault Tolerance of Reversible QCA Circuits 327 -- 12.1 HARDWARE REDUNDANCY TECHNIQUES -- 12.2 MAJORITY MULTIPLEXING IN QCA -- 12.3 REVERSIBLE COMPUTING AND FAULT TOLERANCE -- 12.4 ENERGY DISSIPATION OF A REVERSIBLE MV MULTIPLEXING SYSTEM -- 12.5 CONCLUSION -- References -- Chapter 13 Conclusion and Future Work 349 -- Appendix A Preliminary for QCA Mechanical Model 353 -- References -- Appendix B Validation of Mechanical Model 357 -- B.1 VALIDATION OF STATIC ENERGY ANALYSIS -- B.2 VALIDATION OF DISSIPATION ANALYSIS -- References -- Appendix C Energy Dissipation Analysis of Circuit Units 363 -- About the Authors 367.