C/C++ Based System Design -- How Different Are Esterel and SystemC -- Timed Asynchronous Circuits Modeling and Validation Using SystemC -- On Construction of Cycle Approximate Bus TLMs -- Combinatorial Dependencies in Transaction Level Models -- An Integrated SystemC Debugging Environment -- Measuring the Quality of a SystemC Testbench by Using Code Coverage Techniques -- SystemC-Based Simulation of the MICAS Architecture -- Analog, Mixed-Signal, and Heterogeneous System Design -- Heterogeneous Specification with HetSC and SystemC-AMS: Widening the Support of MoCs in SystemC -- An Extension to VHDL-AMS for AMS Systems with Partial Differential Equations -- Mixed-Level Modeling Using Configurable MOS Transistor Models -- UML-Based System Specification and Design -- Modeling AADL Data Communications with UML MARTE -- Software Real-Time Resource Modeling -- Model Transformations from a Data Parallel Formalism Towards Synchronous Languages -- UML and SystemC – A Comparison and Mapping Rules for Automatic Code Generation -- An Enhanced SystemC UML Profile for Modeling at Transaction-Level -- SC2 StateCharts to SystemC: Automatic Executable Models Generation -- Formalisms for Property-Driven Design -- Asynchronous On-Line Monitoring of Logical and Temporal Assertions -- Transactor-Based Formal Verification of Real-Time Embedded Systems -- A Case-Study in Property-Based Synthesis: Generating a Cache Controller from a Property-Set.