Emerging Nanoelectronic Devices -- Contents -- Preface -- List of Contributors -- Acronyms -- Part One: Introduction -- 1. The Nanoelectronics Roadmap -- 1.1 Introduction -- 1.2 Technology Scaling: Impact and Issues -- 1.3 Technology Scaling: Scaling Limits of Charge-based Devices -- 1.4 The International Technology Roadmap for Semiconductors -- 1.5 ITRS Emerging Research Devices International Technology Working Group -- 1.5.1 ERD Editorial Team -- 1.5.2 Vision and Mission -- 1.5.3 Scope -- 1.6 Guiding Performance Criteria -- 1.6.1 Nanoinformation Processing -- 1.6.2 Nanoelectronic Device Taxonomy -- 1.6.3 Fundamental Guiding Principles - ``Beyond CMOS ́́Information Processing -- 1.6.4 Current Technology Requirements for CMOS Extension and Beyond CMOS Memory and Logic Technologies -- 1.7 Selection of Nanodevices as Technology Entries -- 1.8 Perspectives -- References -- 2. What Constitutes a Nanoswitch? A Perspective -- 2.1 The Search for a Better Switch -- 2.2 Complementary Metal Oxide Semiconductor Switch: Why it Shows Gain -- 2.3 Switch Based on Magnetic Tunnel Junctions: Would it Show Gain? -- 2.3.1 Operation of an MTJ -- 2.3.2 W-R Unit with Electrical Isolation -- 2.3.3 Does This W-R Unit Have Gain? -- 2.4 Giant Spin Hall Effect: A Route to Gain -- 2.4.1 Concatenability -- 2.4.2 Proof of Gain and Directionality -- 2.5 Other Possibilities for Switches with Gain -- 2.5.1 All-spin Logic -- 2.6 What do Alternative Switches Have to Offer? -- 2.6.1 Energy-Delay Product -- 2.6.2 Beyond Boolean Logic -- 2.7 Perspective -- 2.8 Summary -- Acknowledgments -- References -- Part Two: Nanoelectronic Memories -- 3. Memory Technologies: Status and Perspectives -- 3.1 Introduction: Baseline Memory Technologies -- 3.2 Essential Physics of Charge-based Memory -- 3.3 Dynamic Random Access Memory.

3.3.1 Total Energy Required to Create/Maintain the Content of a Memory Cell -- 3.3.2 DRAM Access Time (WRITE or READ) -- 3.3.3 Energy-Space-Time Compromise for DRAM -- 3.4 Flash Memory -- 3.4.1 Store -- 3.4.2 Write -- 3.4.3 Read -- 3.4.4 Energetics of Flash Memory -- 3.5 Static Random Access Memory -- 3.5.1 SRAM Access Time -- 3.5.2 SRAM Scaling -- 3.6 Summary and Perspective -- Appendix: Memory Array Interconnects -- Acknowledgments -- References -- 4. Spin Transfer Torque Random Access Memory -- 4.1 Chapter Overview -- 4.2 Spin Transfer Torque -- 4.2.1 Background of Spin Transfer Torque -- 4.2.2 Experimental Observation of Spin Transfer Torque -- 4.3 STT-RAM Operation -- 4.3.1 Design of STT-RAM Cells -- 4.3.2 Key Parameters for Operation -- 4.4 STT-RAM with Perpendicular Anisotropy -- 4.5 Stack and Material Engineering for Jc Reduction -- 4.5.1 Dual Pinned Structure -- 4.5.2 Nanocurrent Channel Structure Design -- 4.5.3 Electric Field Assisted Switching -- 4.6 Ultra-Fast Switching of MTJs -- 4.7 Spin-Orbit Torques for Memory Application -- 4.8 Current Demonstrations for STT-RAM -- 4.9 Summary and Perspectives -- References -- 5. Phase Change Memory -- 5.1 Introduction -- 5.2 Device Operation -- 5.3 Material Properties -- 5.3.1 Electrical and Phase Transformation Properties -- 5.3.2 Thermal and Mechanical Properties -- 5.4 Device and Material Scaling to the Nanometer Size -- 5.4.1 Materials Scaling Properties -- 5.4.2 Device Scaling Properties -- 5.5 Multi-Bit Operation and 3D Integration -- 5.5.1 Multiple Bits per Element -- 5.5.2 3D Stackable Memory -- 5.6 Applications -- 5.6.1 PCM as a Storage Class Memory -- 5.6.2 PCM as an Electronic Synapse -- 5.7 Future Outlook -- 5.8 Summary -- Acknowledgments -- References -- 6. Ferroelectric FET Memory -- 6.1 Introduction -- 6.2 Ferroelectric FET for Flash Memory Application.

6.2.1 Fe-NAND Flash Memory Operation -- 6.2.2 Nonvolatile Page Buffer -- 6.3 Ferroelectric FET for SRAM Application -- 6.4 System Consideration: SSD System with Fe-NAND Flash Memory -- 6.5 Perspectives and Summary -- References -- 7. Nano-Electro-Mechanical (NEM) Memory Devices -- 7.1 Introduction and Rationale for a Memory Based on NEM Switch -- 7.2 NEM Relay and Capacitor Memories -- 7.3 NEM-FET Memory -- 7.4 Carbon-based NEM Memories -- 7.5 Opportunities and Challenges for NEM Memories -- References -- 8. Redox-based Resistive Memory -- 8.1 Introduction -- 8.2 Physical Fundamentals of Redox Memories -- 8.2.1 Electronic Conduction Mechanisms -- 8.2.2 Ionic Conduction Mechanism -- 8.2.3 Switching Kinetics -- 8.2.4 Generic Switching Properties -- 8.2.5 Modeling Redox Memories for Circuit Simulations -- 8.3 Electrochemical Metallization Memory Cells -- 8.3.1 Physical Switching Mechanism -- 8.3.2 Modeling -- 8.4 Valence Change Memory Cells -- 8.4.1 Physical Switching Mechanism -- 8.4.2 Modeling -- 8.5 Performance -- 8.5.1 Minimum Feature Size -- 8.5.2 Minimum Cell Area -- 8.5.3 Minimum Switching Time -- 8.5.4 Retention Time -- 8.5.5 Write Cycles -- 8.5.6 Multilevel -- 8.6 Summary -- References -- 9. Electronic Effect Resistive Switching Memories -- 9.1 Introduction -- 9.2 Charge Injection and Trapping -- 9.2.1 Charge Trapping Induced Resistive Switching -- 9.2.2 Charge-Trapping Resistive Switching Memory Performance -- 9.3 Mott Transition -- 9.3.1 Resistive Switching Induced by Mott Transition -- 9.3.2 Mott Transition Resistive Switching Memory Performance -- 9.4 Ferroelectric Resistive Switching -- 9.4.1 Ferroelectric Resistive Switching Mechanism -- 9.4.2 Ferroelectric Resistive Switching Memory Performance -- 9.5 Perspectives -- 9.6 Summary -- References -- 10. Macromolecular Memory -- 10.1 Chapter Overview -- 10.2 Macromolecules.

10.2.1 Chemical Structure -- 10.2.2 Memristive Effects in Macromolecular Materials -- 10.2.3 Current State of Macromolecular Memory -- 10.3 Elementary Physical Chemistry of Macromolecular Memory -- 10.3.1 Required Activation Barrier between Stable States -- 10.3.2 Electronic Structure of Macromolecules: Insulators, Semiconductors, Conductors -- 10.3.3 Inducing Changes by Application of Bias Voltage: Electrochemistry -- 10.3.4 Filamentation -- 10.4 Classes of Macromolecular Memory Materials and Their Performance -- 10.4.1 Saturated Macromolecules -- 10.4.2 Macromolecules with π-Conjugation -- 10.5 Perspectives -- 10.6 Summary -- Acknowledgments -- References -- 11. Molecular Transistors -- 11.1 Introduction -- 11.2 Experimental Approaches -- 11.2.1 Fabrication Methods -- 11.2.2 Electronic Transport Fundamentals -- 11.2.3 Molecular Junction Spectroscopies -- 11.3 Molecular Transistors -- 11.3.1 Orbital Gated Transport -- 11.3.2 Coulomb Blockade and Kondo Regimes -- 11.4 Molecular Design -- 11.5 Perspectives -- Acknowledgments -- References -- 12. Memory Select Devices -- 12.1 Introduction -- 12.2 Crossbar Array and Memory Select Devices -- 12.3 Memory Select Device Options -- 12.3.1 Transistors as Memory Select Devices -- 12.3.2 Diodes as Memory Select Devices -- 12.3.3 Volatile Switches as Memory Select Devices -- 12.3.4 Nonlinearity for Device Selection -- 12.4 Challenges of Memory Select Devices -- 12.5 Summary -- References -- 13. Emerging Memory Devices: Assessment and Benchmarking -- 13.1 Introduction -- 13.2 Common Emerging Memory Terminology and Metrics -- 13.3 Redox RAM -- 13.3.1 Electrochemical Metallization Bridge -- 13.3.2 Metal Oxide: Bipolar Filamentary -- 13.3.3 Metal Oxide: Unipolar Filamentary -- 13.3.4 Metal Oxide: Bipolar Nonfilamentary -- 13.4 Emerging Ferroelectric Memories -- 13.4.1 Ferroelectric FET.

13.4.2 Ferroelectric Tunnel Junction -- 13.5 Mott Memory -- 13.6 Macromolecular Memory -- 13.7 Carbon-based Resistive Switching Memory -- 13.7.1 Amorphous Carbon and Diamond-like Carbon -- 13.7.2 Graphene and Graphene Oxide -- 13.7.3 Carbon Nanotubes -- 13.7.4 Research Challenges -- 13.8 Molecular Memory -- 13.9 Assessment and Benchmarking -- 13.9.1 Scaling -- 13.9.2 Performance -- 13.9.3 Reliability -- 13.9.4 CMOS Compatibility and Cost -- 13.9.5 Tradeoffs -- 13.10 Summary and Conclusions -- Acknowledgments -- References -- Part Three: Nanoelectronic Logic and Information Processing -- 14. Re-Invention of FET -- 14.1 Introduction -- 14.2 Historical and Future Trend of MOSFETs -- 14.3 Near-term Solutions -- 14.3.1 High Mobility Channel Transistor -- 14.3.2 Multi-gate Transistor -- 14.3.3 Intrinsic Channel Transistor -- 14.4 Long-term Solutions -- 14.4.1 Energy Efficiency -- 14.4.2 Impact-ionization MOS -- 14.4.3 Tunnel FET -- 14.4.4 Negative Capacitance FET -- 14.4.5 MEMS Switch -- 14.4.6 Mott Transistor -- 14.4.7 Bilayer Pseudo-spin Field-effect Transistor -- 14.5 Summary -- References -- 15. Graphene Electronics -- 15.1 Introduction -- 15.2 Properties of Graphene -- 15.2.1 Bandgap Energy -- 15.2.2 Carrier Transport -- 15.2.3 Heat Transport -- 15.2.4 Contact Resistance -- 15.3 Graphene MOSFETs for Mainstream Logic and RF Applications -- 15.4 Graphene MOSFETs for Nonmainstream Applications -- 15.5 Graphene NonMOSFET Transistors -- 15.6 Perspectives -- 15.6.1 General Remarks -- 15.6.2 Mid-term Perspectives -- 15.6.3 Long-term Future -- Acknowledgment -- References -- 16. Carbon Nanotube Electronics -- 16.1 Carbon Nanotubes - The Ideal Transistor Channel -- 16.1.1 Electronic Structure of a CNT -- 16.1.2 Electron Transport in CNTs -- 16.1.3 The Ideal Transistor -- 16.2 Operation of the CNTFET -- 16.3 Important Aspects of CNTFETs -- 16.3.1 Contacts.

16.3.2 n-Type CNTFETs.