Arithmetic and Logic in Computer Systems -- Contents -- Preface -- List of Figures -- List of Tables -- About the Author -- 1 Computer Number Systems -- 1.1 Conventional Radix Number System -- 1.2 Conversion of Radix Numbers -- 1.3 Representation of Signed Numbers -- 1.3.1 Sign-Magnitude -- 1.3.2 Diminished Radix Complement -- 1.3.3 Radix Complement -- 1.4 Signed-Digit Number System -- 1.5 Floating-point Number Representation -- 1.5.1 Normalization -- 1.5.2 Bias -- 1.6 Residue Number System -- 1.7 Logarithmic Number System -- References -- Problems -- 2 Addition and Subtraction -- 2.1 Single-Bit Adders -- 2.1.1 Logical Devices -- 2.1.2 Single-Bit Half-Adder and Full-Adders -- 2.2 Negation -- 2.2.1 Negation in One's Complement System -- 2.2.2 Negation in Two's Complement System -- 2.3 Subtraction through Addition -- 2.4 Over flow -- 2.5 Ripple Carry Adders -- 2.5.1 Two's Complement Addition -- 2.5.2 One's Complement Addition -- 2.5.3 Sign-Magnitude Addition -- References -- Problems -- 3 High-Speed Adder -- 3.1 Conditional-Sum Addition -- 3.2 Carry-Completion Sensing Addition -- 3.3 Carry-Lookahead Addition (CLA) -- 3.3.1 Carry-Lookahead Adder -- 3.3.2 Block Carry Lookahead Adder -- 3.4 Carry-Save Adders (CSA) -- 3.5 Bit-Partitioned Multiple Addition -- References -- Problems -- 4 Sequential Multiplication -- 4.1 Add-and-shift Approach -- 4.2 Indirect Multiplication Schemes -- 4.2. 1 Unsigned Number Multiplication -- 4.2.2 Sign-Magnitude Number Multiplication -- 4.2.3 One's Complement Number Multiplication -- 4.2.4 Two's Complement Number Multiplication -- 4.3 Robertson's Signed Number Multiplication -- 4.4 Recoding Technique -- 4.4.1 Non-overlapped Multiple Bit Scanning -- 4.4.2 Overlapped Multiple Bit Scanning -- 4.4.3 Booth's Algorithm -- 4.4.4 Canonical Multiplier Recoding -- References -- Problems -- 5 Parallel Multiplication.

5.1 Wallace Trees -- 5.2 Unsigned Array Multiplier -- 5.3 Two's Complement Array Multiplier -- 5.3.1 Baugh- Wooley Two's Complement Multiplier -- 5.3.2 Pezaris Two's Complement Multipliers -- 5.4 Modular Structure of Large Multiplier -- 5.4.1 Modular Structure -- 5.4.2 Additive Multiply Modules -- 5.4.3 Programmable Multiply Modules -- References -- Problems -- 6 Sequential Division -- 6.1 Subtract-and-Shift Approach -- 6.2 Binary Restoring Division -- 6.3 Binary Non-Restoring Division -- 6.4 High-Radix Division -- 6.4.1 High-Radix Non-Restoring Division -- 6.4.2 SRT Division -- 6.4.3 Modified SRT Division -- 6.4.4 Robertson's High-Radix Division -- 6.5 Convergence Division -- 6.5.1 Convergence Division Methodologies -- 6.5.2 Divider Implementing Convergence Division Algorithm -- 6.6 Division by Divisor Reciprocation -- References -- Problems -- 7 Fast Array Dividers -- 7.1 Restoring Cellular Array Divider -- 7.2 Non-Restoring Cellular Array Divider -- 7.3 Carry-Lookahead Cellular Array Divider -- References -- Problems -- 8 Floating Point Operations -- 8.1 Floating Point Addition/Subtraction -- 8.2 Floating Point Multiplication -- 8.3 Floating Point Division -- 8.4 Rounding -- 8.5 Extra Bits -- References -- Problems -- 9 Residue Number Operations -- 9.1 RNS Addition, Subtraction and Multiplication -- 9.2 Number Comparison and Overflow Detection -- 9.2.1 Unsigned Number Comparison -- 9.2.2 Overflow Detection -- 9.2.3 Signed Numbers and Their Properties -- 9.2.4 Multiplicative Inverse and the Parity Table -- 9.3 Division Algorithm -- 9.3.1 Unsigned Number Division -- 9.3.2 Signed Number Division -- 9.3.3 Multiplicative Division Algorithm -- References -- Problems -- 10 Operations through Logarithms -- 10. 1 Multiplication and Addition in Logarithmic Systems -- 10.2 Addition and Subtraction in Logarithmic Systems -- 10.3 Realizing the Approximation.

References -- Problems -- 11 Signed-Digit Number Operations -- 11.1 Characteristics of SD Numbers -- 11.2 Totally Parallel Addition/Subtraction -- 11.3 Required and Allowed Values -- 11.4 Multiplication and Division -- References -- Problems -- Index -- List of Figures -- 1.1 Floating-point Representation -- 1.2 Range of the Numbers -- 1.3 Precision of Floating-Point Numbers -- 1.4 Double Precision Floating-Point Representation -- 2.1 AOI Function -- 2.2 Decoder and Multiplexer -- 2.3 Single-Bit Half-Adder -- 2.4 Design of Full-Adder -- 2.5 Single-Bit Subtrator -- 2.6 Negation in One's Complement System -- 2.7 Negation in Two's Complement System -- 2.8 Subtraction through Addition -- 2.9 One-Bit Adder/Subtractor -- 2.10 Two's Complement Addition/Subtraction -- 2.11 One's Complement Addition/Subtraction -- 2.12 Block Diagram of Sign-Magnitude Addition/Subtraction -- 2.13 Sign-Magnitude Addition/Subtraction -- 3.1 Conditional-Sum Addition -- 3.2 Conditional-Sum Adder -- 3.3 Generation and Transmission of Carries -- 3.4 Construction of Carry-Completion Sensing Adder -- 3.5 Carry-Lookahead Adder -- 3.6 Block Carry-Lookahead Adder -- 3.7 Carry-Save Adder -- 3.8 Carry-Save Adder Tree -- 3.9 Two Types of Parallelization in Multi-Operand Addition -- 3.10 Bit-Partitioned Multiple Addition -- 3.11 Carry-Completion Sensing Adder -- 3.12 Carry-Save Adder -- 3.13 Bit-Partitional Adder -- 4.1 Hardware for Sequential Multiplication -- 4.2 Register Occupation -- 4.3 Unsigned Number Multiplication -- 4.4 Sign -Magn itude Number Multiplication -- 4.5 One's Complement Number Multiplication -- 4.6 Two's Complement Number Multiplication -- 4.7 Negative Multiplicand Times Positive Multiplier -- 4.8 Negative Multiplicand Times Negative Multiplier -- 4.9 Multiple Bit Scanning -- 4.10 String Property -- 4.11 Two-Bit Scan vs. Overlapped Three-Bit Scan.

4.12 Example of Booth's Multiplication -- 4.13 Scan Pattern in 32-bit Multiplication -- 4.14 Adding the Bit-Pairs Parallelly Scanned with a CSA Tree -- 5.1 Wallace Tree -- 5.2 5-by-5 Multiplication -- 5.3 5 × 4 Array Multiplier Perfoming 5-by-5 Multiplication -- 5.4 Different Types of Full Adders -- 5.5 Distribution of Negative Weight -- 5.6 Baugh- Wooley Array Multiplier Perfoming 6-by-4 Two's Complement Multiplication -- 5.7 Baugh- Wooley Multiplication for 10 x (-3) -- 5.8 Baugh-Wooley Array with m=n=5 -- 5.9 Distribution of the Negative Weight -- 5.10 5-by-5 Pezaris Array Multiplier -- 5.11 The Adjustment -- 5.12 5-by-5 Bi-Section Array Multiplier -- 5.13 5-by-5 Tri-section Array Multiplier -- 5.14 Alignment of the Sub-Products -- 5.15 8-by-8 Multiplication via 4-by-4 Multipliers -- 5.16 Modular Structure of Array Multipliers -- 5.17 4-by-2 Additive Multiply Module -- 5.18 8-by-8 Multiplication via 4-by-2 Multipliers -- 5.19 Modular Structure Applying Additive Multiply Modules -- 5.20 Combine Small AMMs into a Large One -- 5.21 Summands of Preparation in Programmable AMM -- 5.22 AMM 8 x 8 Applying AMM 4 x 4 -- 6.1 Pencil-and-Paper Division -- 6.2 Long Division Form -- 6.3 Example of Long Division -- 6.4 Example of Restoring Procedure -- 6.5 Hardware for Restoring Division -- 6.6 Division Performed by Non-Restoring/Restoring Algorithms -- 6.7 Flow Chart for Wilson-Ledley's Division Algorithm -- 6.8 Numerical Example for Wilson-Ledley 's Division Algorithm -- 6.9 Robertson Diagrams -- 6.10 Stepwise Approximation of the Reciprocal of Divisor -- 7.1 4-by-4 Restoring Array Divider -- 7.2 5-by-5 Non-Restoring Array Divider -- 7.3 Carry-Lookahead Array Divider for 4-bit Division (Carry-Lookahead Mechanism is Shown in the Second Row Only) -- 7.4 Example of Carry-Lookahead Array Division -- 7.5 Wires Can Take Up Signifcant Space.

8.1 Data Flow of Floating Point AdditionlSubtraction -- 8.2 Data Flow of Floating Point Multiplication -- 8.3 Data Flow of Floating Point Division -- 8.4 Example of Rounding in Subtraction -- 9.1 Flowchart of the Unsigned Number Division Algorithm -- 9.2 Example of Signed Number Division -- 9.3 Example of Conversion to Mixed-Radix Representation -- 10.1 Linear Approximation of log2 (1 + x) -- 10.2 Mechanism for Multiplication (Division) in Binary Logarithms -- 10.3 Logarithmic Curve and Four-Straight-Line Approximation -- 10.4 Error of the Four-Straight-Line Approximation -- 10.5 Correction Register -- 10.6 Realization of the Correction -- 11.1 Totally-Parallel Adder in Signed-Digit System -- List of Tables -- 1.1 Numbers Represented by 4 bits in Different Number Systems -- 1.2 Finding Signed Digits -- 1.3 Reserved Representation in IEEE Standard -- 2.1 Delay Time and Area of Logic Gates -- 2.2 Logic Function of a Half-Adder -- 2.3 Logic Function of a Full-Adder -- 2.4 Single-Bit Subtractor -- 2.5 Negation in One's Complement System -- 3.1 Maximum Inputs of CSA Trees -- 4.1 Recoding the Triplets -- 5.1 Combination and Delay of k-input Wallace Tree -- 6.1 2-Input 4-Output ROM to Store p 0 (s ). -- 8.1 Round to Nearest Even -- 9.1 Parity Table for Modulus Set {3,5,7} -- 9.2 Mixed-Radix Digits -- 10.1 Required 1/2ps. -- 10.2 Mean-Square Error and Coefficients for Logarithm Approximation -- 10.3 Logarithm Equations -- 11.1 Example for SD Multiplication -- 11.2 Example for SD Division.