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Hennessy, John L.
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-- Memory hierarchy design - Multiprocessors and thread-level parallelism -- Storage systems
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Harris, Sarah L., author.
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Languages -- Digital Building Blocks -- Architecture -- Microarchitecture -- Memory Systems -- I/O Systems
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Farber, Rob.
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. The GPU performance envelope 4. The CUDA memory subsystems 5. Exploiting the CUDA execution grid 6
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Mauerer, Wolfgang, 1978-
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: Memory Management; Chapter 4: Virtual Process Memory; Chapter 5: Locking and Interprocess Communication
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Hennessy, John L.
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: parallelism and memory hierarchy. The six chapters that this book is composed of follow a consistent framework
by
Wilson, G. R. (Graham R.)
ScienceDirect An electronic book accessible through the World Wide Web; click for information
Publisher description http://www.loc.gov/catdir/enhancements/fy0627/2005298841-d.html
Table of contents http://www.loc.gov/catdir/enhancements/fy0627/2005298841-t.html
Publisher description http://www.loc.gov/catdir/enhancements/fy0627/2005298841-d.html
Table of contents http://www.loc.gov/catdir/enhancements/fy0627/2005298841-t.html
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; Cache memory; Memory management; Appendix A G80 instruction set; Appendix B ASCII character codes
by
Mehta, Viranch.
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-- The memory check -- The disk check -- Network devices -- Packet loss and RTA check -- The SNMP status
by
Harris, David Money.
ScienceDirect An electronic book accessible through the World Wide Web; click for information
Table of contents only http://www.loc.gov/catdir/toc/ecip071/2006030554.html
Publisher description http://www.loc.gov/catdir/enhancements/fy0703/2006030554-d.html
Table of contents only http://www.loc.gov/catdir/toc/ecip071/2006030554.html
Publisher description http://www.loc.gov/catdir/enhancements/fy0703/2006030554-d.html
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Description Languages , 5. Digital Building Blocks , 6. Architecture , 7. Microarchitecture , 8. Memory
by
Noergaard, Tammy.
ScienceDirect An electronic book accessible through the World Wide Web; click for information
Publisher description http://www.loc.gov/catdir/enhancements/fy0627/2005297374-d.html
Table of contents http://www.loc.gov/catdir/enhancements/fy0627/2005297374-t.html
Publisher description http://www.loc.gov/catdir/enhancements/fy0627/2005297374-d.html
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, including processors, memory, buses, and I/O system software, including device drivers and operating systems
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Abd-El-Barr, Mostafa.
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II -- 7.1. Main Memory -- 7.2. Virtual Memory -- 7.3. Read-Only Memory -- 7.4. Summary -- Exercises
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El-Rewini, Hesham.
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Methods -- 4.4 Snooping Protocols -- 4.5 Directory Based Protocols -- 4.6 Shared Memory Programming -- 4.7
by
Rochange, Christine.
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. Instruction set extension -- 6.3.3. DDR2 memory controller -- 6.3.4. Conclusion -- 6.4. The multi-issue
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