High-k Gate Dielectrics for CMOS Technology -- Contents -- Preface -- List of Contributors -- Color Plates -- Part One Scaling and Challenge of Si-based CMOS -- 1 Scaling and Limitation of Si-based CMOS -- 1.1 Introduction -- 1.2 Scaling and Limitation of CMOS -- 1.2.1 Device Scaling and Power Dissipation -- 1.2.2 Gate Oxide Tunneling -- 1.2.3 Gate Oxide Scaling Trends -- 1.2.4 Scaling and Limitation of SiO2 Gate Dielectrics -- 1.2.5 Silicon Oxynitrides -- 1.3 Toward Alternative Gate Stacks Technology -- 1.3.1 Advances and Challenges in Dielectric Development -- 1.3.2 Advances and Challenges in Electrode Development -- 1.4 Improvements and Alternative to CMOS Technologies -- 1.4.1 Improvement to CMOS -- 1.4.1.1 New Materials -- 1.4.1.2 New Structures -- 1.5 Potential Technologies Beyond CMOS -- 1.6 Conclusions -- References -- Part Two High-k Deposition and Materials Characterization -- 2 Issues in High-k Gate Dielectrics and its Stack Interfaces -- 2.1 Introduction -- 2.2 High-k Dielectrics -- 2.2.1 The Criteria Required for High-k Dielectrics -- 2.2.2 The Challenges of High-k Dielectrics -- 2.2.2.1 Structural Defects -- 2.2.2.2 Channel Mobility Degradation -- 2.2.2.3 Threshold Voltage Control -- 2.2.2.4 Reliability -- 2.3 Metal Gates -- 2.3.1 Basic Requirements for Metal Gates -- 2.3.2 Metal Gate Materials -- 2.3.2.1 Pure Metals -- 2.3.2.2 Metallic Alloys -- 2.3.2.3 Metal Nitrides -- 2.3.2.4 Metal Silicides -- 2.3.3 Work Function -- 2.3.4 Metal Gate Structures -- 2.3.5 Metal Gate/High-k Integration -- 2.3.6 Process Integration -- 2.4 Integration of High-k Gate Dielectrics with Alternative Channel Materials -- 2.4.1 High-k/Ge Interface -- 2.4.2 High-k/III-V Interface -- 2.5 Summary -- References -- 3 UV Engineering of High-k Thin Films -- 3.1 Introduction -- 3.2 Gas Discharge Generation of UV (Excimer) Radiation.

3.3 Excimer Lamp Sources Based on Silent Discharges -- 3.4 Predeposition Surface Cleaning for High-k Layers -- 3.5 UV Photon Deposition of Ta2O5 Films -- 3.6 Photoinduced Deposition of Hf1-xSixOy Layers -- 3.7 Summary -- References -- 4 Atomic Layer Deposition Process of Hf-Based High-k Gate Dielectric Film on Si Substrate -- 4.1 Introduction -- 4.2 Precursor Effect on the HfO2 Characteristics -- 4.2.1 Hafnium Precursor Effect on the HfO2 Dielectric Characteristics -- 4.2.1.1 Hafnium Chloride (HfCl4) -- 4.2.1.2 Tetrakis Dimethylamido Hafnium [HfN(CH3)2]4 -- 4.2.1.3 Tetrakis Ethylmethylamino Hafnium (Hf[N(C2H5)(CH3)]4) -- 4.2.1.4 tert-Butoxytris[Ethylmethylamido] Hafnium (HfOtBu[NEtMe]3) -- 4.2.1.5 tert-Butoxide Hafnium (Hf[OC4H9]4) -- 4.2.2 Oxygen Sources and Reactants -- 4.2.2.1 H2O versus O3 -- 4.2.2.2 O3 Concentration -- 4.2.2.3 Reactants for In Situ N Incorporation -- 4.3 Doped and Mixed High-k -- 4.3.1 Zr-Doped HfO2 -- 4.3.2 Si-Doped HfO2 -- 4.3.3 Al-Doped HfO2 -- 4.4 Summary -- References -- 5 Structural and Electrical Characteristics of Alternative High-k Dielectrics for CMOS Applications -- 5.1 Introduction -- 5.2 Requirement of High-k Oxide Materials -- 5.3 Rare-Earth Oxide as Alternative Gate Dielectrics -- 5.4 Structural Characteristics of High-k RE Oxide Films -- 5.4.1 Process Compatibility -- 5.4.2 X-Ray Diffraction Analysis -- 5.4.3 Atomic Force Microscope Investigation -- 5.4.4 Transmission Electron Microscopy Technique -- 5.4.5 X-Ray Photoelectron Spectroscopy Analysis -- 5.5 Electrical Characteristics of High-k RE Oxide Films -- 5.5.1 The Threshold Voltage, Flatband Voltage, Interface Trap, and Fixed Charge -- 5.5.2 Leakage Mechanism -- 5.5.2.1 Schottky or Thermionic Emission -- 5.5.2.2 Fowler-Nordheim Tunneling -- 5.5.2.3 Direct Tunneling -- 5.5.2.4 Thermionic Field Emission -- 5.5.2.5 Poole-Frenkel Emission.

5.5.2.6 Hopping Conduction -- 5.5.2.7 Ohmic Conduction -- 5.5.2.8 Space Charge-Limited Conduction -- 5.5.2.9 Ionic Conduction -- 5.5.2.10 Grain Boundary-Limited Conduction -- 5.5.3 High-k Silicon Interface -- 5.5.4 Band Alignment -- 5.5.5 Channel Mobility -- 5.5.6 Dielectric Breakdown -- 5.6 Conclusions and Perspectives -- References -- 6 Hygroscopic Tolerance and Permittivity Enhancement of Lanthanum Oxide (La2O3) for High-k Gate Insulators -- 6.1 Introduction -- 6.2 Hygroscopic Phenomenon of La2O3 Films -- 6.2.1 Effect of Moisture Absorption on Surface Roughness of La2O3 Films -- 6.2.2 Effect of Moisture Absorption on Electrical Properties of La2O3 Films -- 6.3 Low Permittivity Phenomenon of La2O3 Films -- 6.3.1 Moisture Absorption-Induced Permittivity Degradation of La2O3 Films -- 6.3.2 Permittivity of La2O3 Films without Moisture Absorption -- 6.4 Hygroscopic Tolerance Enhancement of La2O3 Films -- 6.4.1 Hygroscopic Tolerance Enhancement of La2O3 Films by Y2O3 Doping -- 6.5 Hygroscopic Tolerance Enhancement of La2O3 Films by Ultraviolet Ozone Treatment -- 6.6 Thermodynamic Analysis of Moisture Absorption Phenomenon in High-k Gate Dielectrics -- 6.7 Permittivity Enhancement of La2O3 Films by Phase Control -- 6.7.1 Experimental Procedures and Characterizations -- 6.7.2 Permittivity Enhancement by Phase Control due to Y2O3 Doping -- 6.7.3 Higher-k Amorphous La1-xTaxOy Films -- 6.8 Summary -- References -- 7 Characterization of High-k Dielectric Internal Structure by X-Ray Spectroscopy and Reflectometry: New Approaches to Interlayer Identification and Analysis -- 7.1 Introduction -- 7.2 Chemical Bonding and Crystalline Structure of Transition Metal Dielectrics -- 7.3 NEXAFS Investigation of Internal Structure -- 7.4 Studying the Internal Structure of High-K Dielectric Films by Hard X-Ray Photoelectron Spectroscopy and TEM.

7.5 Studying the Internal Structure of High-K Dielectric Films by X-ray Reflectometry -- 7.5.1 Reconstruction of the Dielectric Constant Profile by Hard X-Ray Reflectometry -- 7.5.2 Reconstruction of the Depth Distribution of Chemical Elements Concentration by Soft X-Ray Reflectometry -- References -- 8 High-k Insulating Films on Semiconductors and Metals: General Trends in Electron Band Alignment -- 8.1 Introduction -- 8.2 Band Offsets and IPE Spectroscopy -- 8.3 Silicon/Insulator Band Offsets -- 8.4 Band Alignment at Interfaces of High-Mobility Semiconductors -- 8.5 Metal/Insulator Barriers -- 8.6 Conclusions -- References -- Part Three Challenge in Interface Engineering and Electrode -- 9 Interface Engineering in the High-k Dielectric Gate Stacks -- 9.1 Introduction -- 9.2 High-k Oxide/Si Interfaces -- 9.2.1 Growth of Crystalline High-k Oxide on Semiconductors -- 9.2.2 Measurement of Band Alignment at High-k Oxide/Si Interfaces -- 9.3 Metal Gate/High-k Dielectric Interfaces -- 9.4 Chemical Tuning of Band Alignments for Metal Gate/High-k Oxide Interfaces -- 9.5 Summary and Discussion -- References -- 10 Interfacial Dipole Effects on High-k Gate Stacks -- 10.1 Introduction -- 10.2 Metal Gate Consideration -- 10.3 Interfacial Dipole Effects in High-k Gate Stacks -- 10.3.1 Modification of the Gate Work Function by the Interfacial Dipole -- 10.3.2 Fermi-Level Pinning Effects at Gate/High-k Interfaces -- 10.3.3 Micromodels for the Interfacial Dipole in High-k Stacks -- 10.3.3.1 Fermi-Level Pinning -- 10.3.3.2 Oxygen Vacancy Model -- 10.3.3.3 Pauling Electronegativity Model -- 10.3.3.4 Area Oxygen Density Model -- 10.4 Observation of the Interfacial Dipole in High-k Stacks -- 10.4.1 Flatband Voltage Shifts in Capacitance-Voltage Measurements -- 10.4.2 Core-Level Binding Energy Shift in Photoelectron Spectroscopy.

10.4.2.1 Band Discontinuities and Schottky Barrier Analysis in Heterostructures -- 10.4.2.2 Interfacial Charge Investigation -- 10.4.2.3 Band Alignment Determination -- 10.4.2.4 Interfacial Dipole Measurement by Photoelectron Spectroscopy -- 10.4.3 Band Alignments Measured by Using Internal Photoemission -- 10.4.4 Potential Shifts in Kelvin Probe Measurements -- 10.5 Summary -- References -- 11 Metal Gate Electrode for Advanced CMOS Application -- 11.1 The Scaling and Improved Performance of MOSFET Devices -- 11.2 Urgent Issues about MOS Gate Materials for Sub-0.1 mm Device Gate Stack -- 11.2.1 SiO2 Gate Dielectric -- 11.2.2 Polysilicon Electrode -- 11.3 New Requirements of MOS Gate Materials for Sub-0.1 mm Device Gate Stack -- 11.3.1 High-k Gate Dielectric -- 11.3.2 Metal Gate Electrode -- 11.4 Summary -- References -- Part Four Development in non-Si-based CMOS technology -- 12 Metal Gate/High-k CMOS Evolution from Si to Ge Platform -- 12.1 Introduction -- 12.2 High-k/Si CMOSFETs -- 12.2.1 Potential Interface Reaction Mechanism -- 12.2.2 Inserting an Ultrathin SiON -- 12.2.3 Low-Temperature Process -- 12.3 High-k/Ge CMOSFETs -- 12.3.1 Defect-Free Ge-on-Insulator -- 12.3.2 The Challenge for Ge n-MOS -- 12.3.3 High-Mobility Ge n-MOS Using Novel Technology -- 12.4 Ge Platform -- 12.4.1 Logic and Memory Integration -- 12.4.2 3D GeOI/Si IC -- 12.5 Conclusions -- References -- 13 Theoretical Progress on GaAs (001) Surface and GaAs/high-k Interface -- 13.1 Introduction -- 13.2 Computational Method -- 13.3 GaAs Surface Oxidation and Passivation -- 13.3.1 Clean GaAs Surface -- 13.3.2 GaAs Surface Oxidation -- 13.3.3 Passivation of the Oxidized GaAs Surface -- 13.3.4 Initial oxidation of the GaAs(001)-β2(2 x 4) Surface -- 13.4 Origin of Gap States at the High-k/GaAs Interface and Interface Passivation -- 13.4.1 Strained HfO2/GaAs Interface.

13.4.2 Strain-Free GaAs/HfO2 Interfaces.