Cover -- Half-title -- Title -- Copyright -- Contents -- Figures -- Tables -- Preface -- Acknowledgements -- 1 Introduction -- 1.1. Motivation -- 1.2. Book organization -- 2 Synthesizer fundamentals -- 2.1. Introduction -- 2.2. Timing jitter -- 2.3. Phase noise -- 2.4. Phase-locked loop -- 2.4.1. Charge-pump-based phase-locked loop (CP-PLL) -- 2.4.2. Phase noise and jitter of phase-locked loop -- 2.4.3. Spurious tone -- 2.4.4. Settling time -- 2.5. Synthesizer architecture -- 2.5.1. Introduction -- 2.5.2. Integer-N synthesizer -- 2.5.3. Fractional-N synthesizer -- 2.5.4. Dual-loop synthesizer -- 3 Design of building blocks -- 3.1. Voltage-controlled oscillators (VCOs) -- 3.1.1. Ring oscillators -- 3.1.1.1. Circuit implementation -- 3.1.1.2. Phase noise of ring oscillators -- 3.1.2. LC oscillators -- 3.1.2.1. Circuit implementation -- 3.1.2.2. Phase noise of LC oscillators -- 3.1.2.3. Phase-noise analysis -- 3.1.2.4. Quadrature oscillators -- 3.1.2.5. Frequency tuning -- 3.1.2.6. Amplitude modulation to phase modulation noise -- 3.2. Dividers -- 3.2.1. Source-coupled logic divider with resistive load -- 3.2.2. SCL divider with dynamic load -- 3.2.3. Injection-locked frequency divider -- 3.2.4. True single-phase clock divider -- 3.2.5. Divider using static logic -- 3.3. Prescaler -- 3.3.1. Non-programmable prescaler -- 3.3.2. Dual-modulus prescaler -- 3.3.3. Multi-modulus Prescaler -- 3.4. Phase-frequency detectors (PFDs) -- 3.4.1. Phase detector design -- 3.4.2. Phase-frequency detector design -- 3.5. Charge pump -- 3.6. Loop filter -- 3.6.1. Third-order passive loop filter -- 3.6.2. Active loop filter -- 3.7. Inductor design -- 3.7.1. Fundamentals of on-chip inductors -- 3.7.2. Quality factor (Q) of on-chip inductors -- 3.7.3. Design guidelines for on-chip inductors -- 3.8. Varactor design -- 3.8.1. Quality factor (Q) of capacitors.

3.8.2. pn-junction varactors -- 3.8.3. Accumulation-mode varactors -- 3.9. Switched-capacitor array (SCA) -- 4 Low-voltage design considerations and techniques -- 4.1. Introduction -- 4.2. System considerations -- 4.3. Voltage-controlled oscillators -- 4.4. Divide-by-2 circuit -- 4.5. High-speed clock buffer -- 4.6. Prescaler design -- 4.7. Charge pump -- 5 Behavioral simulation -- 5.1. Introduction -- 5.2. Linear model -- 5.3. Mathematical model -- 5.4. Behavioral model using AC analysis -- 5.5. Behavioral model using transient analysis -- 6 A 2 V 900 MHz monolithic CMOS dual-loop frequency synthesizer for GSM receivers -- 6.1. Design specification -- 6.1.1. Output frequency -- 6.1.2. Phase noise -- 6.1.3. Spurious tones -- 6.1.4. Switching time -- 6.1.5. Dual-loop design -- 6.2. Circuit implementation -- 6.2.1. Oscillator VCO2 -- 6.2.1.1. Architecture -- 6.2.1.2. Center frequency and power consumption -- 6.2.1.3. Phase noise -- 6.2.1.4. Design issues -- 6.2.2. Frequency divider N2 and N3 -- 6.2.3. Down-conversion mixer -- 6.2.4. Ring oscillator VCO1 -- 6.2.4.1. Architecture -- 6.2.4.2. Output frequency -- 6.2.4.3. Phase noise -- 6.2.5. Programmable frequency divider N1 -- 6.2.5.1. Architecture and system design -- 6.2.5.2. Dual-modulus prescaler -- 6.2.6. Charge pumps and loop filter -- 6.3. Experimental results -- 6.3.1. Measurement of inductors -- 6.3.2. Measurement of varactors -- 6.3.3. Measurement of ring oscillator VCO1 -- 6.3.4. Measurement of LC oscillator VCO2 -- 6.3.5. Measurement of loop filter -- 6.3.6. Measured phase noise of the frequency synthesizer -- 6.3.7. Measured spurious tones of the frequency synthesizer -- 6.3.8. Switching time of the frequency synthesizer -- 6.3.9. Performance evaluation -- 7 A 1.5 V 900 MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications -- 7.1. Introduction.

7.2. Proposed synthesizer architecture -- 7.3. System speci cation and consideration -- 7.4. Circuit implementation -- 7.4.1. LC VCOs -- 7.4.2. Loop filter -- 7.4.3. Charge pump -- 7.4.4. Phase-frequency detector -- 7.4.5. Prescaler -- 7.4.6. sigma-delta modulator -- 7.4.7. Gain and offset adjustment for SCAs -- 7.5. Layout consideration -- 7.5.1. Switchable-capacitor array -- 7.5.2. Varactor layout -- 7.5.3. Inductor layout -- 7.6. Experimental results -- 7.7. Performance summary and evaluation -- 8 A 1 V 5.2 GHz fully integrated CMOS synthesizer for WLAN IEEE 802.11a -- 8.1. WLAN overview -- 8.2. Design specification -- 8.3. Synthesizer architecture -- 8.4. Quadrature phase generation -- 8.5. Behavioral simulation -- 8.6. Circuit implementation -- 8.6.1. Programmable frequency divider -- 8.6.1.1. Divide-by-2 -- 8.6.1.2. Divide-by-4 -- 8.6.1.3. Phase switching circuits -- 8.6.1.4. Modulus control circuits and phase control circuits -- 8.6.2. Quadrature LC oscillator -- 8.6.3. Loop filter, CPs and PFD -- 8.7. Experimental results -- 8.7.1. Introduction -- 8.7.2. Inductor measurement -- 8.7.3. Measurement of the QVCO -- 8.7.4. Measurement of the synthesizer -- References -- Index.