Front cover -- In Praise of Digital Design and Computer Architecture -- About the Authors -- Title page -- Copyright page -- Table of contents -- Preface -- FEATURES -- ONLINE SUPPLEMENTS -- HOW TO USE THE SOFTWARE TOOLS IN A COURSE -- Xilinx ISE WebPACK -- Synplify Pro -- PCSPIM -- LABS -- BUGS -- ACKNOWLEDGMENTS -- Chapter 1 From Zero to One -- 1.1 THE GAME PLAN -- 1.2 THE ART OF MANAGING COMPLEXITY -- 1.2.1 Abstraction -- 1.2.2 Discipline -- 1.2.3 The Three -Y's -- 1.3 THE DIGITAL ABSTRACTION -- 1.4 NUMBER SYSTEMS -- 1.4.1 Decimal Numbers -- 1.4.2 Binary Numbers -- 1.4.3 Hexadecimal Numbers -- 1.4.4 Bytes, Nibbles, and All That Jazz -- 1.4.5 Binary Addition -- 1.4.6 Signed Binary Numbers -- 1.5 LOGIC GATES -- 1.5.1 NOT Gate -- 1.5.2 Buffer -- 1.5.3 AND Gate -- 1.5.4 OR Gate -- 1.5.5 Other Two-Input Gates -- 1.5.6 Multiple-Input Gates -- 1.6 BENEATH THE DIGITAL ABSTRACTION -- 1.6.1 Supply Voltage -- 1.6.2 Logic Levels -- 1.6.3 Noise Margins -- 1.6.4 DC Transfer Characteristics -- 1.6.5 The Static Discipline -- 1.7 CMOS TRANSISTORS -- 1.7.1 Semiconductors -- 1.7.2 Diodes -- 1.7.3 Capacitors -- 1.7.4 nMOS and pMOS Transistors -- 1.7.5 CMOS NOT Gate -- 1.7.6 Other CMOS Logic Gates -- 1.7.7 Transmission Gates -- 1.7.8 Pseudo-nMOS Logic -- 1.8 POWER CONSUMPTION -- 1.9 SUMMARY AND A LOOK AHEAD -- Exercises -- Interview Questions -- Chapter 2 Combinational Logic Design -- 2.1 INTRODUCTION -- 2.2 BOOLEAN EQUATIONS -- 2.2.1 Terminology -- 2.2.2 Sum-of-Products Form -- 2.2.3 Product-of-Sums Form -- 2.3 BOOLEAN ALGEBRA -- 2.3.1 Axioms -- 2.3.2 Theorems of One Variable -- 2.3.3 Theorems of Several Variables -- 2.3.4 The Truth Behind It All -- 2.3.5 Simplifying Equations -- 2.4 FROM LOGIC TO GATES -- 2.5 MULTILEVEL COMBINATIONAL LOGIC -- 2.5.1 Hardware Reduction -- 2.5.2 Bubble Pushing -- 2.6 X'S AND Z'S, OH MY -- 2.6.1 Illegal Value: X.

2.6.2 Floating Value: Z -- 2.7 KARNAUGH MAPS -- 2.7.1 Circular Thinking -- 2.7.2 Logic Minimization with K-Maps -- 2.7.3 Don't Cares -- 2.7.4 The Big Picture -- 2.8 COMBINATIONAL BUILDING BLOCKS -- 2.8.1 Multiplexers -- 2.8.2 Decoders -- 2.9 TIMING -- 2.9.1 Propagation and Contamination Delay -- 2.9.2 Glitches -- 2.10 SUMMARY -- Exercises -- Interview Questions -- Chapter 3 Sequential Logic Design -- 3.1 INTRODUCTION -- 3.2 LATCHES AND FLIP-FLOPS -- 3.2.1 SR Latch -- 3.2.2 D Latch -- 3.2.3 D Flip-Flop -- 3.2.4 Register -- 3.2.5 Enabled Flip-Flop -- 3.2.6 Resettable Flip-Flop -- 3.2.7 Transistor-Level Latch and Flip-Flop Designs -- 3.2.8 Putting It All Together -- 3.3 SYNCHRONOUS LOGIC DESIGN -- 3.3.1 Some Problematic Circuits -- 3.3.2 Synchronous Sequential Circuits -- 3.3.3 Synchronous and Asynchronous Circuits -- 3.4 FINITE STATE MACHINES -- 3.4.1 FSM Design Example -- 3.4.2 State Encodings -- 3.4.3 Moore and Mealy Machines -- 3.4.4 Factoring State Machines -- 3.4.5 FSM Review -- 3.5 TIMING OF SEQUENTIAL LOGIC -- 3.5.1 The Dynamic Discipline -- 3.5.2 System Timing -- 3.5.3 Clock Skew -- 3.5.4 Metastability -- 3.5.5 Synchronizers -- 3.5.6 Derivation of Resolution Time -- 3.6 PARALLELISM -- 3.7 SUMMARY -- Exercises -- Untitled -- Chapter 4 Hardware Description Languages -- 4.1 INTRODUCTION -- 4.1.1 Modules -- 4.1.2 Language Origins -- 4.1.3 Simulation and Synthesis -- 4.2 COMBINATIONAL LOGIC -- 4.2.1 Bitwise Operators -- 4.2.3 Reduction Operators -- 4.2.2 Comments and White Space -- 4.2.4 Conditional Assignment -- 4.2.5 Internal Variables -- 4.2.6 Precedence -- 4.2.7 Numbers -- 4.2.8 Z's and X's -- 4.2.9 Bit Swizzling -- 4.2.10 Delays -- 4.2.11 VHDL Libraries and Types -- 4.3 STRUCTURAL MODELING -- 4.4 SEQUENTIAL LOGIC -- 4.4.1 Registers -- 4.4.2 Resettable Registers -- 4.4.3 Enabled Registers -- 4.4.4 Multiple Registers -- 4.4.5 Latches.

4.5 MORE COMBINATIONAL LOGIC -- 4.5.1 Case Statements -- 4.5.2 If Statements -- 4.5.3 Verilog casez -- 4.5.4 Blocking and Nonblocking Assignments -- 4.6 FINITE STATE MACHINES -- 4.7 PARAMETERIZED MODULES -- 4.8 TESTBENCHES -- 4.9 SUMMARY -- Exercises -- Verilog Exercises -- VHDL Exercises -- Interview Questions -- Chapter 5 Digital Building Blocks -- 5.1 INTRODUCTION -- 5.2 ARITHMETIC CIRCUITS -- 5.2.1 Addition -- 5.2.2 Subtraction -- 5.2.3 Comparators -- 5.2.4 ALU -- 5.2.5 Shifters and Rotators -- 5.2.6 Multiplication -- 5.2.7 Division -- 5.2.8 Further Reading -- 5.3 NUMBER SYSTEMS -- 5.3.1 Fixed-Point Number Systems -- 5.3.2 Floating-Point Number Systems -- 5.4 SEQUENTIAL BUILDING BLOCKS -- 5.4.1 Counters -- 5.4.2 Shift Registers -- 5.5 MEMORY ARRAYS -- 5.5.1 Overview -- 5.5.2 Dynamic Random Access Memory -- 5.5.3 Static Random Access Memory (SRAM) -- 5.5.4 Area and Delay -- 5.5.5 Register Files -- 5.5.6 Read Only Memory -- 5.5.7 Logic Using Memory Arrays -- 5.5.8 Memory HDL -- 5.6 LOGIC ARRAYS -- 5.6.1 Programmable Logic Array -- 5.6.2 Field Programmable Gate Array -- 5.6.3 Array Implementations -- 5.7 SUMMARY -- Exercises -- Interview Questions -- Chapter 6 Architecture -- 6.1 INTRODUCTION -- 6.2 ASSEMBLY LANGUAGE -- 6.2.1 Instructions -- 6.2.2 Operands: Registers, Memory, and Constants -- 6.3 MACHINE LANGUAGE -- 6.3.1 R-type Instructions -- 6.3.2 I-Type Instructions -- 6.3.3 J-type Instructions -- 6.3.4 Interpreting Machine Language Code -- 6.3.5 The Power of the Stored Program -- 6.4 PROGRAMMING -- 6.4.1 Arithmetic/Logical Instructions -- 6.4.2 Branching -- 6.4.3 Conditional Statements -- 6.4.4 Getting Loopy -- 6.4.5 Arrays -- 6.4.6 Procedure Calls -- 6.5 ADDRESSING MODES -- 6.6 LIGHTS, CAMERA, ACTION: COMPILING, ASSEMBLING, AND LOADING -- 6.6.1 The Memory Map -- 6.6.2 Translating and Starting a Program -- 6.7 ODDS AND ENDS.

6.7.1 Pseudoinstructions -- 6.7.2 Exceptions -- 6.7.3 Signed and Unsigned Instructions -- 6.7.4 Floating-Point Instructions -- 6.8 REAL-WORLD PERSPECTIVE: IA-32 ARCHITECTURE -- 6.8.1 IA-32 Registers -- 6.8.2 IA-32 Operands -- 6.8.3 Status Flags -- 6.8.4 IA-32 Instructions -- 6.8.5 IA-32 Instruction Encoding -- 6.8.6 Other IA-32 Peculiarities -- 6.8.7 The Big Picture -- 6.9 SUMMARY -- Exercises -- Interview Questions -- Chapter 7 Microarchitecture -- 7.1 INTRODUCTION -- 7.1.1 Architectural State and Instruction Set -- 7.1.2 Design Process -- 7.1.3 MIPS Microarchitectures -- 7.2 PERFORMANCE ANALYSIS -- 7.3 SINGLE-CYCLE PROCESSOR -- 7.3.1 Single-Cycle Datapath -- 7.3.2 Single-Cycle Control -- 7.3.3 More Instructions -- 7.3.4 Performance Analysis -- 7.4 MULTICYCLE PROCESSOR -- 7.4.1 Multicycle Datapath -- 7.4.2 Multicycle Control -- 7.4.3 More Instructions -- 7.4.4 Performance Analysis -- 7.5 PIPELINED PROCESSOR -- 7.5.1 Pipelined Datapath -- 7.5.2 Pipelined Control -- 7.5.3 Hazards -- 7.5.4 More Instructions -- 7.5.5 Performance Analysis -- 7.6 HDL REPRESENTATION -- 7.6.1 Single-Cycle Processor -- 7.6.2 Generic Building Blocks -- 7.6.3 Testbench -- 7.7 EXCEPTIONS -- 7.8 ADVANCED MICROARCHITECTURE -- 7.8.1 Deep Pipelines -- 7.8.2 Branch Prediction -- 7.8.3 Superscalar Processor -- 7.8.4 Out-of-Order Processor -- 7.8.5 Register Renaming -- 7.8.6 Single Instruction Multiple Data -- 7.8.7 Multithreading -- 7.8.8 Multiprocessors -- 7.9 REAL-WORLD PERSPECTIVE: IA-32 MICROARCHITECTURE -- 7.10 SUMMARY -- Exercises -- Untitled -- Chapter 8 Memory Systems -- 8.1 INTRODUCTION -- 8.2 MEMORY SYSTEM PERFORMANCE ANALYSIS -- 8.3 CACHES -- 8.3.1 What Data Is Held in the Cache? -- 8.3.2 How Is the Data Found? -- 8.3.3 What Data Is Replaced? -- 8.3.4 Advanced Cache Design -- 8.3.5 The Evolution of MIPS Caches -- 8.4 VIRTUAL MEMORY -- 8.4.1 Address Translation.

8.4.2 The Page Table -- 8.4.3 The Translation Lookaside Buffer -- 8.4.4 Memory Protection -- 8.4.5 Replacement Policies -- 8.4.6 Multilevel Page Tables -- 8.5 MEMORY-MAPPED I/O -- 8.6 REAL-WORLD PERSPECTIVE: IA-32 MEMORY AND I/O SYSTEMS -- 8.6.1 IA-32 Cache Systems -- 8.6.2 IA-32 Virtual Memory -- 8.6.3 IA-32 Programmed I/O -- 8.7 SUMMARY -- EPILOGUE -- Exercises -- Interview Questions -- Appendix A Digital System Implementation -- A .1 INTRODUCTION -- A.2 74XX LOGIC -- A.2.1 Logic Gates -- A.2.2 Other Functions -- A.3 PROGRAMMABLE LOGIC -- A.3.1 PROMs -- A.3.2 PLAs -- A.3.3 FPGAs -- A.4 APPLICATION-SPECIFIC INTEGRATED CIRCUITS -- A.5 DATA SHEETS -- A.6 LOGIC FAMILIES -- A.7 PACKAGING AND ASSEMBLY -- A.8 TRANSMISSION LINES -- A.8.1 Matched Termination -- A.8.2 Open Termination -- A.8.3 Short Termination -- A.8.4 Mismatched Termination -- A.8.5 When to Use Transmission Line Models -- A.8.6 Proper Transmission Line Terminations -- A.8.7 Derivation of Z0 -- A.8.8 Derivation of the Reflection Coefficient -- A.8.9 Putting It All Together -- A.9 ECONOMICS -- Appendix B MIPS Instructions -- Further Reading -- Index.