FRONT COVER -- COMPLETE PCB DESIGN USING ORCAD CAPTURE AND LAYOUT -- COPYRIGHT PAGE -- TABLE OF CONTENTS -- INTRODUCTION -- ACKNOWLEDGMENTS -- CHAPTER 1: INTRODUCTION TO PCB DESIGN AND CAD -- Computer-Aided Design and the OrCAD Design Suite -- Printed Circuit Board Fabrication -- PCB cores and layer stack-up -- PCB fabrication process -- Photolithography and chemical etching -- Mechanical milling -- Layer registration -- Function of OrCAD Layout in the PCB Design Process -- Design Files Created by Layout -- Layout format files (.MAX) -- Postprocess (Gerber) files -- PCB assembly layers and files -- CHAPTER 2: INTRODUCTION TO THE PCB DESIGN FLOW BY EXAMPLE -- Overview of the Design Flow -- Creating a Circuit Design with Capture -- Starting a new project -- Placing parts -- Wiring (connecting) the parts -- Creating the Layout netlist in Capture -- Designing the PCB with Layout -- Starting Layout and importing the netlist -- Making a board outline -- Placing the parts -- Autorouting the board -- Manual routing -- Cleanup -- Locking traces -- Performing a design rule check -- Postprocessing the board design for manufacturing -- CHAPTER 3: PROJECT STRUCTURES AND THE LAYOUT TOOL SET -- Project Setup and Schematic Entry Details -- Capture projects explained -- Capture part libraries explained -- Understanding the Layout Environment and Tool Set -- Board technology files -- The AutoECO utility -- The session frame and Design window -- The toolbar -- Controlling the autorouter -- Postprocessing and layer details -- CHAPTER 4: INTRODUCTION TO INDUSTRY STANDARDS -- Introduction to the Standards Organizations -- Institute for Printed Circuits (IPC-Association Connecting Electronics Industries) -- Electronic Industries Alliance (EIA) -- Joint Electron Device Engineering Council (JEDEC) -- International Engineering Consortium (IEC) -- Military Standards.

American National Standards Institute (ANSI) -- Institute of Electrical and Electronics Engineers (IEEE) -- Classes and Types of PCBs -- Performance classes -- Producibility levels -- Fabrication types and assembly subclasses -- OrCAD Layout design complexity levels-IPC performance classes -- IPC land pattern density levels -- Introduction to Standard Fabrication Allowances -- Registration tolerances -- Breakout and annular ring control -- PCB Dimensions and Tolerances -- Standard panel sizes -- Tooling area allowances and effective panel usage -- Standard finished PCB thickness -- Core thickness -- Prepreg thickness -- Copper thickness for PTHs and vias -- Copper cladding/foil thickness -- Copper Trace and Etching Tolerances -- Standard Hole Dimensions -- Soldermask Tolerance -- End Note -- Suggested reading -- Other items of interest -- CHAPTER 5: INTRODUCTION TO DESIGN FOR MANUFACTURING -- Introduction to PCB Assembly and Soldering Processes -- Assembly Processes -- Manual assembly processes -- Automated assembly processes (pick and place) -- Soldering Processes -- Manual soldering -- Wave soldering -- Reflow soldering -- Component Placement and Orientation Guide -- Component Spacing for Through-hole Devices -- Discrete THDs -- Integrated circuit through-hole devices -- Mixed discrete and IC through-hole devices -- Holes and jumper wires -- Component Spacing for Surface-Mounted Devices -- Discrete SMDs -- Integrated-circuit SMDs -- Mixed discrete and IC SMDs -- Mixed THD and SMD Spacing Requirements -- Footprint and Padstack Design for PCB Manufacturability -- Land Patterns for Surface-Mounted Devices -- SMD padstack design -- SMD footprint design -- Land Patterns for Through-hole Devices -- Footprint design for through-hole devices -- Padstack design for through-hole devices -- Hole-to-lead ratio -- PTH land dimension (annular ring width).

Clearance between plane layers and PTHs -- Soldermask and solder paste dimensions -- CHAPTER 6: PCB DESIGN FOR SIGNAL INTEGRITY -- Circuit Design Issues Not Related to PCB Layout -- Noise -- Distortion -- Frequency response -- Issues Related to PBC Layout -- Electromagnetic Interference and Cross Talk -- Magnetic fields and inductive coupling -- Loop inductance -- Electric fields and capacitive coupling -- Ground Planes and Ground Bounce -- What ground is and what it is not -- Ground (return) planes -- Ground bounce and rail collapse -- Split power and ground planes -- PCB Electrical Characteristics -- Characteristic impedance -- Reflections -- Ringing -- Electrically long traces -- Critical length -- Transmission line terminations -- PCB Routing Topics -- Parts placement for electrical considerations -- PCB layer stack-up -- Bypass capacitors and fanout -- Trace width for current carrying capability -- Trace width for controlled impedance -- Trace spacing for voltage withstanding -- Trace spacing to minimize cross talk (3w rule) -- Traces with acute and 90º angles -- CHAPTER 7: MAKING AND EDITING CAPTURE PARTS -- The Capture Part Libraries -- Types of Packaging -- Homogeneous parts -- Heterogeneous parts -- Pins -- Part Editing Tools -- The Select tool and settings -- The pin tools -- The graphics tools -- The zoom tools -- Constructing Capture Parts -- Method 1: Constructing Parts Using the New Part Option (Design Menu) -- Design example for a passive, homogeneous part -- Design example for an active, multipart, homogeneous component -- Assigning power pin visibility -- Design example for a passive, heterogeneous part -- Method 2: Constructing Parts with Capture Using the Design Spreadsheet -- Method 3: Constructing Parts Using Generate Part from the Tools Menu -- Method 4: Generating Parts with the PSpice Model Editor.

Generating a Capture part library from a PSpice model library -- Making and/or Obtaining PSpice Libraries for Making New Capture Parts -- Downloading libraries and/or models from the Internet -- Making a PSpice model from a Capture project -- Adding PSpice templates (models) to preexisting Capture parts -- Constructing Capture Symbols -- CHAPTER 8: MAKING AND EDITING LAYOUT FOOTPRINTS -- Introduction to the Library Manager -- Introduction to Layout's Footprint Libraries and Naming Conventions -- Layout's footprint libraries -- Naming conventions -- The Composition of Footprints -- Padstacks -- Obstacles -- Text -- Datums and insertion origins -- The Basic Footprint Design Process -- Working with Padstacks -- Accessing existing padstacks -- Editing padstack properties from the spreadsheet -- Saving footprints and padstacks -- Footprint Design Examples -- Design example 1: a surface-mount footprint design -- Design example 2: a modified through-hole footprint design -- Using the Pad Array Generator -- Introduction -- Footprint design for PGAs -- Footprint design for BGAs -- Blind, buried, and microvias -- Mounting holes -- Printing a catalog of a footprint library -- CHAPTER 9: PCB DESIGN EXAMPLES -- Overview of the Design Flow -- Example 1: Dual Power Supply, Analog Design -- Initial design concept and preparation -- Project setup and design in Capture -- Defining the board requirements -- Importing the design into Layout -- Setting up the board -- Prerouting the board -- Autorouting the board -- Finalizing the design -- Example 2: Mixed Analog/Digital Design Using Split Power, Ground Planes -- Mixed-signal circuit design in Capture -- Power and ground connections to digital and analog parts -- Connecting separate analog and digital grounds to a split plane -- Using busses for digital nets -- Defining the layer stack-up for split planes.

Establishing a primary power plane -- Creating split ground planes -- Creating nested power planes with copper pours -- Using anti-copper on plane layers -- Setting up and running the autorouter -- Moving a routed trace to a different layer -- Adding ground planes and guard traces to routing layers -- Defining vias for flood planes/pours -- Setting the copper pour spacing -- Stitching a ground plane manually -- Using anti-copper obstacles on copper pours -- Routing guard traces and rings -- Example 3: Multipage, Multipower, and Multiground Mixed A/D PCB Design with PSpice -- Project setup for PSpice simulation and Layout -- Adding schematic pages to the design -- Using off-page connectors with wires -- Using off-page connectors with busses -- Setting up multiple-ground systems -- Setting up PSpice sources -- Performing PSpice simulations -- Preparing the simulated project for Layout -- Assigning a new technology file -- Placing parts on the bottom (back) of a board -- Layer stack-up for a multiground system -- Net layer assignments -- Through-hole and blind via setup -- Fanning out a board with multiple vias -- Overriding known errors in Layout -- Autorouting with the DRC/route box -- Using forced thermals to connect ground planes -- Using the AutoECO to update a board from Capture -- Example 4: High-Speed Digital Design -- Layer setup for microstrip transmission lines -- Via design for heat spreaders -- Constructing a heat spreader with copper area obstacles -- Using free vias as heat pipes -- Determining critical trace length of transmission lines -- Routing controlled impedance traces -- Moated ground areas for clock circuits -- Routing curved traces -- Gate and pin swapping -- Stitching a ground plane with the free via matrix -- Miscellaneous Items -- Fixing bad pad exits -- Design cache-cleanup, replace, update -- Adding test points.

Types of AutoECOs.