ESD Failure Mechanisms and Models -- Contents -- About the Author -- Preface -- Acknowledgments -- 1 Failure Analysis and ESD -- 1.1 INTRODUCTION -- 1.1.1 FA Techniques for Evaluation of ESD Events -- 1.1.2 Fundamental Concepts of ESD FA Methods and Practices -- 1.1.3 ESD Failure: Why Do Semiconductor Chips Fail? -- 1.1.4 How to Use FA to Design ESD Robust Technologies -- 1.1.5 How to Use FA to Design ESD Robust Circuits -- 1.1.6 How to Use FA for Temperature Prediction -- 1.1.7 How to Use Failure Models for Power Prediction -- 1.1.8 FA Methods, Design Rules, and ESD Ground Rules -- 1.1.9 FA and Semiconductor Process-Induced ESD Design Asymmetry -- 1.1.10 FA Methodology and Electro-thermal Simulation -- 1.1.11 FA and ESD Testing Methodology -- 1.1.12 FA Methodology for Evaluation of ESD Parasitics -- 1.1.13 FA Methods and ESD Device Operation Verification -- 1.1.14 FA Methodology to Evaluate Inter-power Rail Electrical Connectivity -- 1.1.15 How to Use FA to Eliminate Failure Mechanisms -- 1.2 ESD FAILURE: HOW DO MICRO-ELECTRONIC DEVICES FAIL? -- 1.2.1 ESD Failure: How Do Metallurgical Junctions Fail? -- 1.2.2 ESD Failure: How Do Insulators Fail? -- 1.2.3 ESD Failure: How Do Metals Fail? -- 1.3 SENSITIVITY OF SEMICONDUCTOR COMPONENTS -- 1.3.1 ESD Sensitivity as a Function of Materials -- 1.3.2 ESD Sensitivity as a Function of Semiconductor Devices -- 1.3.3 ESD Sensitivity as a Function of Product Type -- 1.3.4 ESD and Technology Scaling -- 1.3.5 ESD Technology Roadmap -- 1.4 HOW DO SEMICONDUCTOR CHIPS FAIL--ARE THE FAILURES RANDOM OR SYSTEMATIC? -- 1.5 CLOSING COMMENTS AND SUMMARY -- PROBLEMS -- REFERENCES -- 2 Failure Analysis Tools, Models, and Physics of Failure -- 2.1 FA TECHNIQUES FOR EVALUATION OF ESD EVENTS -- 2.2 FA TOOLS -- 2.2.1 Optical Microscope -- 2.2.2 Scanning Electron Microscope -- 2.2.3 Transmission Electron Microscope.

2.2.4 Emission Microscope -- 2.2.5 Thermally Induced Voltage Alteration -- 2.2.6 Superconducting Quantum Interference Device Microscope -- 2.2.7 Atomic Force Microscope -- 2.2.8 The 2-D AFM -- 2.2.9 Picosecond Current Analysis Tool -- 2.2.10 Transmission Line Pulse--Picosecond Current Analysis Tool -- 2.3 ESD SIMULATION: ESD PULSE MODELS -- 2.3.1 Human Body Model -- 2.3.2 Machine Model -- 2.3.3 Cassette Model -- 2.3.4 Socketed Device Model -- 2.3.5 Charged Board Model -- 2.3.6 Cable Discharge Event -- 2.3.7 IEC System-Level Pulse Model -- 2.3.8 Human Metal Model -- 2.3.9 Transmission Line Pulse Testing -- 2.3.10 Very Fast Transmission Line Pulse (VF-TLP) Model -- 2.3.11 Ultra-fast Transmission Line Pulse (UF-TLP) Model -- 2.4 ELECTRO-THERMAL PHYSICAL MODELS -- 2.4.1 Tasca Model -- 2.4.2 Wunsch-Bell Model -- 2.4.3 Smith-Littau Model -- 2.4.4 Ash Model -- 2.4.5 Arkihpov, Astvatsaturyan, Godovosyn, and Rudenko Model -- 2.4.6 Dwyer, Franklin, and Campbell Model -- 2.4.7 Vlasov-Sinkevitch Model -- 2.5 STATISTICAL MODELS FOR ESD PREDICTION -- 2.6 CLOSING COMMENTS AND SUMMARY -- PROBLEMS -- REFERENCES -- 3 CMOS Failure Mechanisms -- 3.1 TABLES OF CMOS ESD FAILURE MECHANISMS -- 3.2 LOCOS ISOLATION-DEFINED CMOS -- 3.2.1 LOCOS-Bound Structures -- 3.2.2 LOCOS-Bound P+/N-well Junction Diode -- 3.2.3 LOCOS-Bound N+/P- Substrate Junction Diode -- 3.2.4 LOCOS-Bound N-well/P- Substrate Junction Diode -- 3.2.5 LOCOS-Bound Lateral N-well to N-well -- 3.2.6 LOCOS-Bound Lateral N+ to N-well -- 3.2.7 LOCOS-Bound Lateral PNP Bipolar -- 3.2.8 LOCOS-Bound Thick Oxide MOSFET -- 3.3 SHALLOW TRENCH ISOLATION (STI) -- 3.3.1 STI Pull-down ESD Failure Mechanism -- 3.3.2 STI Pull-down and Gate Wrap-around -- 3.3.3 Silicides and Diodes -- 3.3.4 Non-silicide Diode Structures -- 3.3.5 STI-Defined P+/N-well Diode -- 3.3.6 STI-Defined N-well to Substrate Diode.

3.3.7 STI Lateral N-well to N-well NPN Structures -- 3.4 POLYSILICON-DEFINED DEVICES -- 3.4.1 Polysilicon-Bound Gated Diode -- 3.5 LATERAL DIODE WITH BLOCK MASK -- 3.6 MOSFETs -- 3.6.1 N-channel MOSFETs -- 3.6.2 N-channel Multi-finger MOSFETs -- 3.6.3 Cascoded Series N-channel MOSFETs -- 3.6.4 P-channel MOSFETs -- 3.6.5 P-channel Multi-finger MOSFETs -- 3.6.6 Tungsten Silicide Gate MOSFET -- 3.6.7 Polysilicon Silicide Gate MOSFET -- 3.6.8 Metal Gate/High k Dielectric MOSFET -- 3.7 RESISTORS -- 3.7.1 Diffused Resistors -- 3.7.2 N-well Resistors -- 3.7.3 Buried Resistors -- 3.7.4 Silicide Blocked N-diffusion Resistors -- 3.8 INTERCONNECTS: WIRES, VIAS, AND CONTACTS -- 3.8.1 Aluminum Interconnects -- 3.8.2 Copper Interconnects -- 3.8.3 Tungsten Interconnects -- 3.8.4 Vias -- 3.8.5 Contacts -- 3.9 ESD FAILURE IN CMOS NANOSTRUCTURES -- 3.9.1 ESD Failures in 130 nm Technology -- 3.9.2 ESD Failures in 90 nm Technology -- 3.9.3 ESD Failures in 65 nm Technology -- 3.9.4 ESD Failures in 45 nm Technology -- 3.9.5 ESD Failures in 32 nm Technology -- 3.9.6 ESD Failures in 22 nm Technology -- 3.10 CLOSING COMMENTS AND SUMMARY -- PROBLEMS -- REFERENCES -- 4 CMOS Circuits: Receivers and Off-Chip Drivers -- 4.1 TABLES OF CMOS RECEIVER AND OCD ESD FAILURE MECHANISMS -- 4.2 RECEIVER CIRCUITS -- 4.3 RECEIVER CIRCUITS WITH ESD NETWORKS -- 4.3.1 Receiver with Dual Diode and Series Resistor -- 4.3.2 Receiver with Diode-Resistor-Diode -- 4.3.3 Receiver with Diode-Resistor-MOSFET -- 4.4 RECEIVER CIRCUITS WITH HALF-PASS TRANSMISSION GATE -- 4.5 RECEIVER WITH FULL-PASS TRANSMISSION GATE -- 4.5.1 Receiver with Full-Pass Transmission Gate with Second Power Source -- 4.6 RECEIVER, HALF-PASS TRANSMISSION GATE, AND KEEPER NETWORK -- 4.6.1 Receiver, Half-Pass Transmission Gate, and the Modified Keeper Network -- 4.7 RECEIVER CIRCUITS WITH PSEUDO-ZERO VT HALF-PASS TRANSMISSION GATE.

4.8 RECEIVER WITH ZERO VT TRANSMISSION GATE -- 4.9 RECEIVER CIRCUITS WITH BLEED TRANSISTORS -- 4.10 RECEIVER CIRCUITS WITH TEST FUNCTIONS -- 4.11 RECEIVER WITH SCHMITT TRIGGER FEEDBACK NETWORKS -- 4.12 OFF-CHIP DRIVERS -- 4.12.1 OCD Design Process-Related ESD Failure -- 4.13 SINGLE NFET PULL-DOWN OCD -- 4.14 SERIES CASCODE MOSFETs -- 4.15 I/O DESIGN CONSIDERATIONS AND ESD PARASITIC FAILURE MECHANISMS -- 4.15.1 Layout-Dependent ESD Failure Mechanisms -- 4.16 CLOSING COMMENTS AND SUMMARY -- PROBLEMS -- REFERENCES -- 5 CMOS Integration -- 5.1 TABLE OFCMOSINTEGRATION ESD FAILURE MECHANISMS -- 5.2 ARCHITECTURE AND DESIGN SYNTHESIS-RELATED FAILURES -- 5.3 ALTERNATE CURRENT LOOP -- 5.4 CHIP CAPACITANCE -- 5.5 ESD POWER CLAMPS -- 5.6 INTRA- AND INTER-DOMAIN ESD PROTECTION -- 5.7 SPLIT GROUND CONFIGURATIONS -- 5.8 MIXED VOLTAGE INTERFACE -- 5.8.1 Peripheral VCC and Core VDD Power Rails -- 5.8.2 Two Power Supply: Peripheral and Core VDD Power Rails -- 5.8.3 Voltage Regulators -- 5.9 MIXED SIGNAL INTERFACE -- 5.9.1 Digital and Analog -- 5.9.2 Digital, Analog, and RF -- 5.10 INTER-DOMAIN SIGNAL LINE ESD FAILURES -- 5.10.1 Digital-to-Analog Signal Line Failures -- 5.11 DECOUPLING CAPACITORS -- 5.12 SYSTEM CLOCK AND PHASE-LOCKED LOOP -- 5.13 FUSE NETWORKS -- 5.13.1 Fuse Networks and ESD Failure Mechanisms -- 5.13.2 eFUSE and ESD Failure Mechanisms -- 5.14 BOND PADS -- 5.14.1 Floating Bond Pads -- 5.14.2 Floating Bond Pads over Interconnects -- 5.14.3 Bond Pad Failure: Programmable VDD -- 5.14.4 Bond Pad to Bond Pad ESD Failures -- 5.14.5 Bond Pad Failure: ESD Structures under Bond Pads -- 5.15 MOSFET GATE STRUCTURE -- 5.15.1 MOSFET Floating Gate and Floating Gate Tie Down -- 5.15.2 MOSFET Gates Connected to Power VDD -- 5.16 FILL SHAPES -- 5.17 NO CONNECTS -- 5.18 TEST CIRCUITRY -- 5.19 MULTI-CHIP SYSTEMS -- 5.19.1 Multi-chip Systems on Multi-layer Ceramic.

5.19.2 Multi-chip Systems and Silicon Carriers -- 5.19.3 Multi-chip Systems: Chip-to-Chip Failures with Adjacent Chips -- 5.19.4 Multi-chip Systems: Proximity Communications -- 5.20 CMOS LATCHUP FAILURES -- 5.20.1 Table of Latchup Failures -- 5.20.2 Latchup Failure Mechanisms -- 5.21 CLOSING COMMENTS AND SUMMARY -- PROBLEMS -- REFERENCES -- 6 SOI ESD Failure Mechanisms -- 6.1 TABLES OF SOI DEVICE AND INTEGRATION ESD FAILURE MECHANISMS -- 6.2 SOI N-CHANNEL MOSFETs -- 6.2.1 SOI Single-Finger N-channel MOSFETs -- 6.2.2 SOI Multi-finger MOSFETs -- 6.3 SOI DIODES -- 6.3.1 SOI Poly-bound Gated Diode -- 6.3.2 SOI Poly-bound Gated Diode with Halo Implants -- 6.4 SOI BURIED RESISTORS -- 6.5 SOI FAILURE MECHANISMS IN 150NM TECHNOLOGY -- 6.5.1 Lateral Graded Gated SOI Diode Structure -- 6.5.2 Lateral Ungated SOI Diode Structure -- 6.6 SOI ESD FAILURE MECHANISMS IN 45NM TECHNOLOGY -- 6.6.1 SOI Lateral Gated Diode -- 6.6.2 SOI Double-Well Field Effect Device -- 6.6.3 SOI: ESD under BOX -- 6.7 SOI ESD FAILURE MECHANISMS IN 32NM TECHNOLOGY -- 6.8 SOI ESD FAILURE MECHANISMS IN 22NM TECHNOLOGY AND THE FUTURE -- 6.9 SOI DESIGN SYNTHESIS AND ESD FAILURE MECHANISMS -- 6.9.1 SOI ESD Circuit Failure Mechanisms -- 6.9.2 Mixed Voltage SOI ESD Circuit Failure Mechanisms -- 6.9.3 SOI Receiver Network ESD Failures -- 6.9.4 SOI Fuse Networks -- 6.9.5 SOI Dynamic Threshold Circuitry -- 6.9.6 SOI Active Clamp Circuitry -- 6.10 SOI INTEGRATION: ESD FAILURE MECHANISMS -- 6.11 CLOSING COMMENTS AND SUMMARY -- PROBLEMS -- REFERENCES -- 7 RF CMOS and ESD -- 7.1 TABLES OF RF CMOS ESD FAILURE MECHANISMS -- 7.2 RF MOSFET -- 7.3 RF SHALLOW TRENCH ISOLATION DIODE -- 7.4 RF POLYSILICON GATED DIODE -- 7.5 SILICON-CONTROLLED RECTIFIER -- 7.6 SCHOTTKY BARRIER DIODES -- 7.7 CAPACITORS -- 7.7.1 MIM Capacitor -- 7.7.2 Varactors and Hyper-abrupt Varactor Capacitors.

7.7.3 Metal-ILD-Metal Capacitor.