Search Results for - Narrowed by: Schwiegelshohn, Uwe. editor. - Logic design.
SirsiDynix Enterprise
https://catalog.iyte.edu.tr/client/en_US/default/default/qf$003dAUTHOR$002509Author$002509Schwiegelshohn$00252C$002bUwe.$002beditor.$002509Schwiegelshohn$00252C$002bUwe.$002beditor.$0026qf$003dSUBJECT$002509Subject$002509Logic$002bdesign.$002509Logic$002bdesign.$0026ps$003d300$0026isd$003dtrue?
2024-06-20T01:54:43Z
Job Scheduling Strategies for Parallel Processing 13th International Workshop, JSSPP 2007, Seattle, WA, USA, June 17, 2007. Revised Papers
ent://SD_ILS/0/SD_ILS:503412
2024-06-20T01:54:43Z
2024-06-20T01:54:43Z
by Frachtenberg, Eitan. editor.<br/><a href="http://dx.doi.org/10.1007/978-3-540-78699-3">http://dx.doi.org/10.1007/978-3-540-78699-3</a><br/>Format: Electronic Resources<br/>
Job Scheduling Strategies for Parallel Processing 12th International Workshop, JSSPP 2006, Saint-Malo, France, June 26, 2006, Revised Selected Papers
ent://SD_ILS/0/SD_ILS:512270
2024-06-20T01:54:43Z
2024-06-20T01:54:43Z
by Frachtenberg, Eitan. editor.<br/><a href="http://dx.doi.org/10.1007/978-3-540-71035-6">http://dx.doi.org/10.1007/978-3-540-71035-6</a><br/>Format: Electronic Resources<br/>
Job Scheduling Strategies for Parallel Processing 10th International Workshop, JSSPP 2004, New York, NY, USA, June 13, 2004. Revised Selected Papers
ent://SD_ILS/0/SD_ILS:510185
2024-06-20T01:54:43Z
2024-06-20T01:54:43Z
by Feitelson, Dror G. editor.<br/><a href="http://dx.doi.org/10.1007/b107134">http://dx.doi.org/10.1007/b107134</a><br/>Format: Electronic Resources<br/>
Job Scheduling Strategies for Parallel Processing 11th International Workshop, JSSPP 2005, Cambridge, MA, USA, June 19, 2005, Revised Selected Papers
ent://SD_ILS/0/SD_ILS:510089
2024-06-20T01:54:43Z
2024-06-20T01:54:43Z
by Feitelson, Dror. editor.<br/><a href="http://dx.doi.org/10.1007/11605300">http://dx.doi.org/10.1007/11605300</a><br/>Format: Electronic Resources<br/>