Search Results for - Narrowed by: Logic design. - Arithmetic and Logic Structures.SirsiDynix Enterprisehttps://catalog.iyte.edu.tr/client/en_US/default/default/qf$003dSUBJECT$002509Subject$002509Logic$002bdesign.$002509Logic$002bdesign.$0026qf$003dSUBJECT$002509Subject$002509Arithmetic$002band$002bLogic$002bStructures.$002509Arithmetic$002band$002bLogic$002bStructures.$0026ps$003d300?2024-06-14T13:50:41ZAlgorithms and Architectures for Parallel Processing 18th International Conference, ICA3PP 2018, Guangzhou, China, November 15-17, 2018, Proceedings, Part IIIent://SD_ILS/0/SD_ILS:20853892024-06-14T13:50:41Z2024-06-14T13:50:41Zby Vaidya, Jaideep. editor.<br/><a href="https://doi.org/10.1007/978-3-030-05057-3">https://doi.org/10.1007/978-3-030-05057-3</a><br/>Format: Electronic Resources<br/>Algorithms and Architectures for Parallel Processing 18th International Conference, ICA3PP 2018, Guangzhou, China, November 15-17, 2018, Proceedings, Part Ient://SD_ILS/0/SD_ILS:20855432024-06-14T13:50:41Z2024-06-14T13:50:41Zby Vaidya, Jaideep. editor.<br/><a href="https://doi.org/10.1007/978-3-030-05051-1">https://doi.org/10.1007/978-3-030-05051-1</a><br/>Format: Electronic Resources<br/>Logical Foundations of Computer Science International Symposium, LFCS 2018, Deerfield Beach, FL, USA, January 8–11, 2018, Proceedingsent://SD_ILS/0/SD_ILS:20850462024-06-14T13:50:41Z2024-06-14T13:50:41Zby Artemov, Sergei. editor.<br/><a href="https://doi.org/10.1007/978-3-319-72056-2">https://doi.org/10.1007/978-3-319-72056-2</a><br/>Format: Electronic Resources<br/>Computational Autisment://SD_ILS/0/SD_ILS:20847862024-06-14T13:50:41Z2024-06-14T13:50:41Zby Galitsky, Boris. author.<br/><a href="https://doi.org/10.1007/978-3-319-39972-0">https://doi.org/10.1007/978-3-319-39972-0</a><br/>Format: Electronic Resources<br/>Guide to Discrete Mathematics An Accessible Introduction to the History, Theory, Logic and Applicationsent://SD_ILS/0/SD_ILS:20845262024-06-14T13:50:41Z2024-06-14T13:50:41Zby O'Regan, Gerard. author.<br/><a href="https://doi.org/10.1007/978-3-319-44561-8">https://doi.org/10.1007/978-3-319-44561-8</a><br/>Format: Electronic Resources<br/>High Performance Embedded Architectures and Compilers Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008. Proceedingsent://SD_ILS/0/SD_ILS:5032652024-06-14T13:50:41Z2024-06-14T13:50:41Zby Stenström, Per. editor.<br/><a href="http://dx.doi.org/10.1007/978-3-540-77560-7">http://dx.doi.org/10.1007/978-3-540-77560-7</a><br/>Format: Electronic Resources<br/>Transactions on High-Performance Embedded Architectures and Compilers Ient://SD_ILS/0/SD_ILS:5123572024-06-14T13:50:41Z2024-06-14T13:50:41Zby Stenström, Per. editor.<br/><a href="http://dx.doi.org/10.1007/978-3-540-71528-3">http://dx.doi.org/10.1007/978-3-540-71528-3</a><br/>Format: Electronic Resources<br/>Advances in Computer Systems Architecture 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007. Proceedingsent://SD_ILS/0/SD_ILS:5127762024-06-14T13:50:41Z2024-06-14T13:50:41Zby Choi, Lynn. editor.<br/><a href="http://dx.doi.org/10.1007/978-3-540-74309-5">http://dx.doi.org/10.1007/978-3-540-74309-5</a><br/>Format: Electronic Resources<br/>Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007. Proceedingsent://SD_ILS/0/SD_ILS:5127872024-06-14T13:50:41Z2024-06-14T13:50:41Zby Azémard, Nadine. editor.<br/><a href="http://dx.doi.org/10.1007/978-3-540-74442-9">http://dx.doi.org/10.1007/978-3-540-74442-9</a><br/>Format: Electronic Resources<br/>High Performance Embedded Architectures and Compilers Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedingsent://SD_ILS/0/SD_ILS:5121562024-06-14T13:50:41Z2024-06-14T13:50:41Zby Bosschere, Koen. editor.<br/><a href="http://dx.doi.org/10.1007/978-3-540-69338-3">http://dx.doi.org/10.1007/978-3-540-69338-3</a><br/>Format: Electronic Resources<br/>Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedingsent://SD_ILS/0/SD_ILS:5116302024-06-14T13:50:41Z2024-06-14T13:50:41Zby Vounckx, Johan. editor.<br/><a href="http://dx.doi.org/10.1007/11847083">http://dx.doi.org/10.1007/11847083</a><br/>Format: Electronic Resources<br/>Advances in Computer Systems Architecture 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006. Proceedingsent://SD_ILS/0/SD_ILS:5116592024-06-14T13:50:41Z2024-06-14T13:50:41Zby Jesshope, Chris. editor.<br/><a href="http://dx.doi.org/10.1007/11859802">http://dx.doi.org/10.1007/11859802</a><br/>Format: Electronic Resources<br/>Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedingsent://SD_ILS/0/SD_ILS:5104402024-06-14T13:50:41Z2024-06-14T13:50:41Zby Paliouras, Vassilis. editor.<br/><a href="http://dx.doi.org/10.1007/11556930">http://dx.doi.org/10.1007/11556930</a><br/>Format: Electronic Resources<br/>High Performance Embedded Architectures and Compilers First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005. Proceedingsent://SD_ILS/0/SD_ILS:5105482024-06-14T13:50:41Z2024-06-14T13:50:41Zby Conte, Tom. editor.<br/><a href="http://dx.doi.org/10.1007/11587514">http://dx.doi.org/10.1007/11587514</a><br/>Format: Electronic Resources<br/>Advances in Computer Systems Architecture 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005. Proceedingsent://SD_ILS/0/SD_ILS:5104672024-06-14T13:50:41Z2024-06-14T13:50:41Zby Srikanthan, Thambipillai. editor.<br/><a href="http://dx.doi.org/10.1007/11572961">http://dx.doi.org/10.1007/11572961</a><br/>Format: Electronic Resources<br/>