Search Results for - Narrowed by: Systems engineering. - Computer aided design.SirsiDynix Enterprisehttps://catalog.iyte.edu.tr/client/en_US/default/default/qf$003dSUBJECT$002509Subject$002509Systems$002bengineering.$002509Systems$002bengineering.$0026qf$003dSUBJECT$002509Subject$002509Computer$002baided$002bdesign.$002509Computer$002baided$002bdesign.$0026ps$003d300?2024-05-30T00:01:51ZMillimeter-Wave Low Noise Amplifiersent://SD_ILS/0/SD_ILS:20868102024-05-30T00:01:51Z2024-05-30T00:01:51Zby Božanić, Mladen. author.<br/><a href="https://doi.org/10.1007/978-3-319-69020-9">https://doi.org/10.1007/978-3-319-69020-9</a><br/>Format: Electronic Resources<br/>VLSI-SoC: Design for Reliability, Security, and Low Power 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected Papersent://SD_ILS/0/SD_ILS:20847662024-05-30T00:01:51Z2024-05-30T00:01:51Zby Shin, Youngsoo. editor.<br/><a href="https://doi.org/10.1007/978-3-319-46097-0">https://doi.org/10.1007/978-3-319-46097-0</a><br/>Format: Electronic Resources<br/>Power Amplifiers for the S-, C-, X- and Ku-bands An EDA Perspectiveent://SD_ILS/0/SD_ILS:20877362024-05-30T00:01:51Z2024-05-30T00:01:51Zby Božanić, Mladen. author.<br/><a href="https://doi.org/10.1007/978-3-319-28376-0">https://doi.org/10.1007/978-3-319-28376-0</a><br/>Format: Electronic Resources<br/>System Verilog for Verification A Guide to Learning the Testbench Language Featuresent://SD_ILS/0/SD_ILS:5018762024-05-30T00:01:51Z2024-05-30T00:01:51Zby Spear, Chris. author.<br/><a href="http://dx.doi.org/10.1007/978-0-387-76530-3">http://dx.doi.org/10.1007/978-0-387-76530-3</a><br/>Format: Electronic Resources<br/>Low-Power High-Level Synthesis for Nanoscale CMOS Circuitsent://SD_ILS/0/SD_ILS:5018702024-05-30T00:01:51Z2024-05-30T00:01:51Zby Patra, Priyardarsan. author.<br/><a href="http://dx.doi.org/10.1007/978-0-387-76474-0">http://dx.doi.org/10.1007/978-0-387-76474-0</a><br/>Format: Electronic Resources<br/>CMOS Active Inductors and Transformers Principle, Implementation, and Applicationsent://SD_ILS/0/SD_ILS:5018722024-05-30T00:01:51Z2024-05-30T00:01:51Zby Yuan, Fei. author.<br/><a href="http://dx.doi.org/10.1007/978-0-387-76479-5">http://dx.doi.org/10.1007/978-0-387-76479-5</a><br/>Format: Electronic Resources<br/>Nanometer Technology Designs High-Quality Delay Testsent://SD_ILS/0/SD_ILS:5018452024-05-30T00:01:51Z2024-05-30T00:01:51Zby Tehranipoor, Mohammad. author.<br/><a href="http://dx.doi.org/10.1007/978-0-387-75728-5">http://dx.doi.org/10.1007/978-0-387-75728-5</a><br/>Format: Electronic Resources<br/>Functional Verification Coverage Measurement and Analysisent://SD_ILS/0/SD_ILS:5022022024-05-30T00:01:51Z2024-05-30T00:01:51Zby Piziali, Andrew. author.<br/><a href="http://dx.doi.org/10.1007/b117979">http://dx.doi.org/10.1007/b117979</a><br/>Format: Electronic Resources<br/>Rapid Prototyping of Digital Systemsent://SD_ILS/0/SD_ILS:5017092024-05-30T00:01:51Z2024-05-30T00:01:51Zby Hamblen, James O. author.<br/><a href="http://dx.doi.org/10.1007/978-0-387-72671-7">http://dx.doi.org/10.1007/978-0-387-72671-7</a><br/>Format: Electronic Resources<br/>Power Distribution Networks with On-Chip Decoupling Capacitorsent://SD_ILS/0/SD_ILS:5016732024-05-30T00:01:51Z2024-05-30T00:01:51Zby Popovich, Mikhhail. author.<br/><a href="http://dx.doi.org/10.1007/978-0-387-71601-5">http://dx.doi.org/10.1007/978-0-387-71601-5</a><br/>Format: Electronic Resources<br/>Creating Assertion-Based IPent://SD_ILS/0/SD_ILS:5016092024-05-30T00:01:51Z2024-05-30T00:01:51Zby Foster, Harry D. author.<br/><a href="http://dx.doi.org/10.1007/978-0-387-68398-0">http://dx.doi.org/10.1007/978-0-387-68398-0</a><br/>Format: Electronic Resources<br/>Design for Manufacturability and Statistical Design A Constructive Approachent://SD_ILS/0/SD_ILS:5016402024-05-30T00:01:51Z2024-05-30T00:01:51Zby Orshansky, Michael. author.<br/><a href="http://dx.doi.org/10.1007/978-0-387-69011-7">http://dx.doi.org/10.1007/978-0-387-69011-7</a><br/>Format: Electronic Resources<br/>Standardized Functional Verificationent://SD_ILS/0/SD_ILS:5016752024-05-30T00:01:51Z2024-05-30T00:01:51Zby Wiemann, Alan. author.<br/><a href="http://dx.doi.org/10.1007/978-0-387-71733-3">http://dx.doi.org/10.1007/978-0-387-71733-3</a><br/>Format: Electronic Resources<br/>Inverse Problems in Electric Circuits and Electromagneticsent://SD_ILS/0/SD_ILS:5055972024-05-30T00:01:51Z2024-05-30T00:01:51Zby Chechurin, V. L. author.<br/><a href="http://dx.doi.org/10.1007/978-0-387-46047-5">http://dx.doi.org/10.1007/978-0-387-46047-5</a><br/>Format: Electronic Resources<br/>Routing Congestion in VLSI Circuits: Estimation and Optimizationent://SD_ILS/0/SD_ILS:5056772024-05-30T00:01:51Z2024-05-30T00:01:51Zby Saxena, Prashant. author.<br/><a href="http://dx.doi.org/10.1007/0-387-48550-3">http://dx.doi.org/10.1007/0-387-48550-3</a><br/>Format: Electronic Resources<br/>Verilog and SystemVerilog Gotchas 101 Common Coding Errors and How to Avoid Thement://SD_ILS/0/SD_ILS:5059702024-05-30T00:01:51Z2024-05-30T00:01:51Zby Sutherland, Stuart. author.<br/><a href="http://dx.doi.org/10.1007/978-0-387-71715-9">http://dx.doi.org/10.1007/978-0-387-71715-9</a><br/>Format: Electronic Resources<br/>Hardware Verification with SystemVerilog An Object-Oriented Frameworkent://SD_ILS/0/SD_ILS:5059752024-05-30T00:01:51Z2024-05-30T00:01:51Zby Mintz, Mike. author.<br/><a href="http://dx.doi.org/10.1007/978-0-387-71740-1">http://dx.doi.org/10.1007/978-0-387-71740-1</a><br/>Format: Electronic Resources<br/>Global Specification and Validation of Embedded Systems Integrating Heterogeneous Componentsent://SD_ILS/0/SD_ILS:5075542024-05-30T00:01:51Z2024-05-30T00:01:51Zby Nicolescu, G. editor.<br/><a href="http://dx.doi.org/10.1007/978-1-4020-6153-0">http://dx.doi.org/10.1007/978-1-4020-6153-0</a><br/>Format: Electronic Resources<br/>Full-Chip Nanometer Routing Techniquesent://SD_ILS/0/SD_ILS:5075672024-05-30T00:01:51Z2024-05-30T00:01:51Zby Ho, Tsung-Yi. author.<br/><a href="http://dx.doi.org/10.1007/978-1-4020-6195-0">http://dx.doi.org/10.1007/978-1-4020-6195-0</a><br/>Format: Electronic Resources<br/>Dynamics of Microelectromechanical Systemsent://SD_ILS/0/SD_ILS:5057852024-05-30T00:01:51Z2024-05-30T00:01:51Zby Lobontiu, Nicolae. author.<br/><a href="http://dx.doi.org/10.1007/978-0-387-68195-5">http://dx.doi.org/10.1007/978-0-387-68195-5</a><br/>Format: Electronic Resources<br/>Systematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based Systems on Heterogeneous Platformsent://SD_ILS/0/SD_ILS:5076232024-05-30T00:01:51Z2024-05-30T00:01:51Zby Ma, Zhe. editor.<br/><a href="http://dx.doi.org/10.1007/978-1-4020-6344-2">http://dx.doi.org/10.1007/978-1-4020-6344-2</a><br/>Format: Electronic Resources<br/>Design for Manufacturability and Yield for Nano-Scale CMOSent://SD_ILS/0/SD_ILS:5071742024-05-30T00:01:51Z2024-05-30T00:01:51Zby Chiang, Charles C. author.<br/><a href="http://dx.doi.org/10.1007/978-1-4020-5188-3">http://dx.doi.org/10.1007/978-1-4020-5188-3</a><br/>Format: Electronic Resources<br/>CMOS Current-Mode Circuits for Data Communicationsent://SD_ILS/0/SD_ILS:5056532024-05-30T00:01:51Z2024-05-30T00:01:51Zby Yuan, Fei. author.<br/><a href="http://dx.doi.org/10.1007/978-0-387-47691-9">http://dx.doi.org/10.1007/978-0-387-47691-9</a><br/>Format: Electronic Resources<br/>SAT-Based Scalable Formal Verification Solutionsent://SD_ILS/0/SD_ILS:5058662024-05-30T00:01:51Z2024-05-30T00:01:51Zby Ganai, Malay K. author.<br/><a href="http://dx.doi.org/10.1007/978-0-387-69167-1">http://dx.doi.org/10.1007/978-0-387-69167-1</a><br/>Format: Electronic Resources<br/>Closing the Power Gap Between ASIC & Custom Tools and Techniques for Low Power Designent://SD_ILS/0/SD_ILS:5058472024-05-30T00:01:51Z2024-05-30T00:01:51Zby Chinnery, David. author.<br/><a href="http://dx.doi.org/10.1007/978-0-387-68953-1">http://dx.doi.org/10.1007/978-0-387-68953-1</a><br/>Format: Electronic Resources<br/>Verification Methodology Manual for SystemVerilogent://SD_ILS/0/SD_ILS:5044112024-05-30T00:01:51Z2024-05-30T00:01:51Zby Bergeron, Janick. author.<br/><a href="http://dx.doi.org/10.1007/b135575">http://dx.doi.org/10.1007/b135575</a><br/>Format: Electronic Resources<br/>Semiconductor Modeling For Simulating Signal, Power, and Electromagnetic Integrityent://SD_ILS/0/SD_ILS:5042732024-05-30T00:01:51Z2024-05-30T00:01:51Zby Leventhal, Roy G. author.<br/><a href="http://dx.doi.org/10.1007/b104647">http://dx.doi.org/10.1007/b104647</a><br/>Format: Electronic Resources<br/>Abstraction Refinement for Large Scale Model Checkingent://SD_ILS/0/SD_ILS:5053222024-05-30T00:01:51Z2024-05-30T00:01:51Zby Wang, Chao. author.<br/><a href="http://dx.doi.org/10.1007/0-387-34600-7">http://dx.doi.org/10.1007/0-387-34600-7</a><br/>Format: Electronic Resources<br/>The Core Test Wrapper Handbook Rationale and Application of IEEE Std. 1500™ent://SD_ILS/0/SD_ILS:5053242024-05-30T00:01:51Z2024-05-30T00:01:51Zby Silva, Francisco. author.<br/><a href="http://dx.doi.org/10.1007/0-387-34609-0">http://dx.doi.org/10.1007/0-387-34609-0</a><br/>Format: Electronic Resources<br/>SystemVerilog for Design A Guide to Using SystemVerilog for Hardware Design and Modelingent://SD_ILS/0/SD_ILS:5054242024-05-30T00:01:51Z2024-05-30T00:01:51Zby Sutherland, Stuart. author.<br/><a href="http://dx.doi.org/10.1007/0-387-36495-1">http://dx.doi.org/10.1007/0-387-36495-1</a><br/>Format: Electronic Resources<br/>Interconnect Noise Optimization in Nanometer Technologiesent://SD_ILS/0/SD_ILS:5049062024-05-30T00:01:51Z2024-05-30T00:01:51Zby Elgamel, Mohamed A. author.<br/><a href="http://dx.doi.org/10.1007/0-387-29366-3">http://dx.doi.org/10.1007/0-387-29366-3</a><br/>Format: Electronic Resources<br/>Writing Testbenches using System Verilogent://SD_ILS/0/SD_ILS:5050752024-05-30T00:01:51Z2024-05-30T00:01:51Zby Bergeron, Janick. author.<br/><a href="http://dx.doi.org/10.1007/0-387-31275-7">http://dx.doi.org/10.1007/0-387-31275-7</a><br/>Format: Electronic Resources<br/>Systemverilog for Verification A Guide to Learning the Testbench Language Featuresent://SD_ILS/0/SD_ILS:5045712024-05-30T00:01:51Z2024-05-30T00:01:51Zby Spear, Chris. author.<br/><a href="http://dx.doi.org/10.1007/b138536">http://dx.doi.org/10.1007/b138536</a><br/>Format: Electronic Resources<br/>Rapid Prototyping of Digital Systemsent://SD_ILS/0/SD_ILS:5048552024-05-30T00:01:51Z2024-05-30T00:01:51Zby Hamblen, James O. author.<br/><a href="http://dx.doi.org/10.1007/0-387-28965-8">http://dx.doi.org/10.1007/0-387-28965-8</a><br/>Format: Electronic Resources<br/>Electromagnetic Compatibility of Integrated Circuits Techniques for low emission and susceptibilityent://SD_ILS/0/SD_ILS:5045452024-05-30T00:01:51Z2024-05-30T00:01:51Zby Ben Dhia, Sonia. editor.<br/><a href="http://dx.doi.org/10.1007/b137864">http://dx.doi.org/10.1007/b137864</a><br/>Format: Electronic Resources<br/>Constraint-Based Verificationent://SD_ILS/0/SD_ILS:5050262024-05-30T00:01:51Z2024-05-30T00:01:51Zby Yuan, Jun. author.<br/><a href="http://dx.doi.org/10.1007/0-387-30784-2">http://dx.doi.org/10.1007/0-387-30784-2</a><br/>Format: Electronic Resources<br/>Leakage in Nanometer CMOS Technologiesent://SD_ILS/0/SD_ILS:5047372024-05-30T00:01:51Z2024-05-30T00:01:51Zby Narendra, Siva G. author.<br/><a href="http://dx.doi.org/10.1007/0-387-28133-9">http://dx.doi.org/10.1007/0-387-28133-9</a><br/>Format: Electronic Resources<br/>Embedded System Designent://SD_ILS/0/SD_ILS:5049672024-05-30T00:01:51Z2024-05-30T00:01:51Zby Marwedel, Peter. author.<br/><a href="http://dx.doi.org/10.1007/0-387-30087-2">http://dx.doi.org/10.1007/0-387-30087-2</a><br/>Format: Electronic Resources<br/>Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platformsent://SD_ILS/0/SD_ILS:5070292024-05-30T00:01:51Z2024-05-30T00:01:51Zby Kogel, Tim. author.<br/><a href="http://dx.doi.org/10.1007/1-4020-4826-2">http://dx.doi.org/10.1007/1-4020-4826-2</a><br/>Format: Electronic Resources<br/>Reuse-Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuitsent://SD_ILS/0/SD_ILS:5071542024-05-30T00:01:51Z2024-05-30T00:01:51Zby CASTRO-LÓPEZ, R. author.<br/><a href="http://dx.doi.org/10.1007/978-1-4020-5139-5">http://dx.doi.org/10.1007/978-1-4020-5139-5</a><br/>Format: Electronic Resources<br/>A Roadmap for Formal Property Verificationent://SD_ILS/0/SD_ILS:5070052024-05-30T00:01:51Z2024-05-30T00:01:51Zby DasGupta, Pallab. author.<br/><a href="http://dx.doi.org/10.1007/978-1-4020-4758-9">http://dx.doi.org/10.1007/978-1-4020-4758-9</a><br/>Format: Electronic Resources<br/>Hardware Verification with C++ A Practitioner’s Handbookent://SD_ILS/0/SD_ILS:5054122024-05-30T00:01:51Z2024-05-30T00:01:51Zby Mintz, Mike. author.<br/><a href="http://dx.doi.org/10.1007/978-0-387-36254-0">http://dx.doi.org/10.1007/978-0-387-36254-0</a><br/>Format: Electronic Resources<br/>Thermal and Power Management of Integrated Circuitsent://SD_ILS/0/SD_ILS:5049422024-05-30T00:01:51Z2024-05-30T00:01:51Zby Vassighi, Arman. author.<br/><a href="http://dx.doi.org/10.1007/0-387-29749-9">http://dx.doi.org/10.1007/0-387-29749-9</a><br/>Format: Electronic Resources<br/>Scalable Hardware Verification with Symbolic Simulationent://SD_ILS/0/SD_ILS:5049572024-05-30T00:01:51Z2024-05-30T00:01:51Zby Bertacco, Valeria. author.<br/><a href="http://dx.doi.org/10.1007/0-387-29906-8">http://dx.doi.org/10.1007/0-387-29906-8</a><br/>Format: Electronic Resources<br/>Taxonomies for the Development and Verification of Digital Systemsent://SD_ILS/0/SD_ILS:5042532024-05-30T00:01:51Z2024-05-30T00:01:51Zby Bailey, Brian. editor.<br/><a href="http://dx.doi.org/10.1007/b104217">http://dx.doi.org/10.1007/b104217</a><br/>Format: Electronic Resources<br/>Mixed-Signal Layout Generation Conceptsent://SD_ILS/0/SD_ILS:5040472024-05-30T00:01:51Z2024-05-30T00:01:51Zby Lin, Chieh. author.<br/><a href="http://dx.doi.org/10.1007/b106472">http://dx.doi.org/10.1007/b106472</a><br/>Format: Electronic Resources<br/>Advances in Design and Specification Languages for SoCs Selected Contributions from FDL’04ent://SD_ILS/0/SD_ILS:5044942024-05-30T00:01:51Z2024-05-30T00:01:51Zby Boulet, Pierre. editor.<br/><a href="http://dx.doi.org/10.1007/b136935">http://dx.doi.org/10.1007/b136935</a><br/>Format: Electronic Resources<br/>Digital Design and Implementation with Field Programmable Devicesent://SD_ILS/0/SD_ILS:5076902024-05-30T00:01:51Z2024-05-30T00:01:51Zby Navabi, Zainalabedin. author.<br/><a href="http://dx.doi.org/10.1007/b117975">http://dx.doi.org/10.1007/b117975</a><br/>Format: Electronic Resources<br/>Assertion-Based Designent://SD_ILS/0/SD_ILS:5076912024-05-30T00:01:51Z2024-05-30T00:01:51Zby Foster, Harry. author.<br/><a href="http://dx.doi.org/10.1007/b117047">http://dx.doi.org/10.1007/b117047</a><br/>Format: Electronic Resources<br/>Direct Transistor-level Layout for Digital Blocksent://SD_ILS/0/SD_ILS:5076922024-05-30T00:01:51Z2024-05-30T00:01:51Zby Gopalakrishnan, Prakash. author.<br/><a href="http://dx.doi.org/10.1007/b117054">http://dx.doi.org/10.1007/b117054</a><br/>Format: Electronic Resources<br/>SystemC Kernel Extensions for Heterogeneous System Modeling A framework for Multi-MoC Modeling & Simulationent://SD_ILS/0/SD_ILS:5076962024-05-30T00:01:51Z2024-05-30T00:01:51Zby Patel, Hiren D. author.<br/><a href="http://dx.doi.org/10.1007/b117249">http://dx.doi.org/10.1007/b117249</a><br/>Format: Electronic Resources<br/>Interconnect-Centric Design for Advanced SoC and NoCent://SD_ILS/0/SD_ILS:5076832024-05-30T00:01:51Z2024-05-30T00:01:51Zby Nurmi, Jari. editor.<br/><a href="http://dx.doi.org/10.1007/b117241">http://dx.doi.org/10.1007/b117241</a><br/>Format: Electronic Resources<br/>Functional Verification of Programmable Embedded Architectures A Top-Down Approachent://SD_ILS/0/SD_ILS:5045342024-05-30T00:01:51Z2024-05-30T00:01:51Zby Mishra, Prabhat. author.<br/><a href="http://dx.doi.org/10.1007/b137514">http://dx.doi.org/10.1007/b137514</a><br/>Format: Electronic Resources<br/>