Advanced Circuits FOR Emerging Technologies -- CONTENTS -- Preface -- Contributors -- PART I: DIGITAL DESIGN AND POWER MANAGEMENT -- 1 DESIGN IN THE ENERGY-DELAY SPACE -- 1.1 Introduction -- 1.2 Energy and Delay Modeling -- 1.2.1 Delay: the Logical Effort as a Modeling Approach -- 1.2.2 Delay: the Logical Effort as an Optimization Approach -- 1.2.3 Energy: A Comprehensive Model -- 1.3 Energy-Delay Space Analysis and Hardware-Intensity -- 1.3.1 The Energy-Efficient Curve -- 1.3.2 Energy-Delay Metrics and Hardware Intensity -- 1.3.3 Voltage Intensity and Generalization of the Sensitivity Criterion -- 1.4 Energy-Efficient Design of Digital Circuits -- 1.4.1 The Role of the Input Capacitance -- 1.4.2 Definition of Design Space Bounds -- 1.4.3 Simulations-Based Optimization of Small Size Circuits -- 1.4.4 Nonlinear and Convex Optimization of Large Size Circuits -- 1.5 Design of Energy-Efficient Pipelined Systems -- 1.5.1 Zyuban and Strenski's Hardware-Voltage Intensity Criteria -- 1.5.1.1 A Composite Pipeline Stage -- 1.5.1.2 A Multistage Pipeline -- 1.5.1.3 A Multistage Pipeline with Composite Stages -- 1.5.2 Practical Guidelines to Design Energy-Efficient Pipelines -- 1.6 Conclusion -- References -- 2 SUBTHRESHOLD SOURCE-COUPLED LOGIC -- 2.1 Introduction -- 2.2 Ultralow Power CMOS Logic: Design and Tradeoffs -- 2.2.1 Conventional Design Approach -- 2.2.2 Static Power Dissipation -- 2.2.3 Process Variation -- 2.2.3.1 Noise Margin -- 2.2.3.2 Reducing Supply Voltage Versus Using High-VT Devices -- 2.3 Subthreshold Source-Coupled Logic -- 2.3.1 Introduction -- 2.3.2 Circuit Topology -- 2.3.2.1 Conventional SCL -- 2.3.2.2 Subthreshold SCL -- 2.3.2.3 Power-Delay Performance -- 2.4 Power-Frequency Scaling -- 2.4.1 Introduction -- 2.4.2 Tuning System -- 2.5 Conclusions -- References.

3 ULTRALOW-VOLTAGE DESIGN OF NANOMETER CMOS CIRCUITS FOR SMART ENERGY-AUTONOMOUS SYSTEMS -- 3.1 Introduction -- 3.2 Impact of Technology Scaling on Subthreshold MOSFET Characteristics -- 3.2.1 Subthreshold Current -- 3.2.2 Subthreshold Variability -- 3.2.3 Subthreshold Gate Capacitance -- 3.3 Scaling Trend of the Minimum-Energy Point -- 3.3.1 Theory of the Minimum-Energy Point -- 3.3.2 Minimum-Energy Point in Nanometer CMOS Technologies -- 3.3.2.1 DIBL Effect -- 3.3.2.2 Gate Leakage -- 3.3.2.3 Cycle Time Guardband Due to WID Variability -- 3.3.2.4 Leakage Overhead Due to WID Variability -- 3.3.3 Technology/Circuit Solutions to Keep Minimum-Energy Under Control -- 3.3.3.1 Optimum MOSFET Selection for Circuit Designers -- 3.3.3.2 Fully Depleted SOI for Technology Developers -- 3.4 Practical Energy of Nanometer ULV Circuits under Robustness and Timing Constraints -- 3.4.1 Functional Limit on the Supply Voltage -- 3.4.1.1 Noise Margin Violations -- 3.4.1.2 Hold Time Violations -- 3.4.2 Process Flavor Selection for Minimum Energy Under Timing Constraints -- 3.4.3 Circuit Adaptation for Minimization of Cycle Time Guardband -- 3.5 Technology/Circuit Methodology and Roadmap for ULV Design in the Nanometer Era -- 3.5.1 Reducing Emin -- 3.5.2 Reaching Emin -- 3.5.3 Technology/Circuit Roadmap -- 3.6 Conclusion -- References -- 4 IMPAIRMENT-AWARE ANALOG CIRCUIT DESIGN BY RECONFIGURING FEEDBACK SYSTEMS -- 4.1 Introduction -- 4.2 Theorem of Impairment-Aware Analog Design in Feedback Systems -- 4.3 Practical Implementations -- 4.3.1 Design of Impairment-Aware Loop Gain in Charge Pump PLL -- 4.3.2 Design of Impairment-Aware Stability in Digital Controlled Oscillator-Based CDR -- 4.3.3 Calibration of DCO Gain in ADPLL -- 4.3.4 Design of Impairment-Aware Two-Point Modulator -- 4.3.5 Impairment-Aware DAC in Sigma-Delta ADC -- 4.4 Measured Results.

4.4.1 Impairment-Aware Loop Gain in Pre-Emphasis Transmitter -- 4.4.2 Impairment-Aware Two-Point Modulator -- 4.5 Conclusions -- References -- 5 ROM-BASED LOGIC DESIGN: A LOW-POWER DESIGN PERSPECTIVE -- 5.1 Introduction -- 5.2 RBL Design -- 5.2.1 Fast Single Transistor ROM Cell -- 5.2.2 ROM Size Reduction -- 5.2.3 Dynamic ROM-Based Design -- 5.3 RBL Adder -- 5.3.1 RBL Carry Select Adder -- 5.3.2 RBL Conditional Sum Adder -- 5.4 RBL Multiplier -- 5.4.1 4 × 4 ROM Multiplier Design: the Basic Block -- 5.4.2 Carry Save Adder Design -- 5.4.3 Analysis -- 5.5 Conclusions -- References -- 6 POWER MANAGEMENT: ENABLING TECHNOLOGY -- 6.1 Macroeconomic Drivers for Power Technologies -- 6.1.1 Energy Conservation -- 6.1.2 Power-Conversion Efficiency -- 6.1.3 Portable Power -- 6.2 Market Trends -- 6.2.1 Power Management Semiconductors Compound Annual Growth -- 6.3 Application Examples -- 6.3.1 Energy Conservation -- 6.3.2 Power Conversion and Efficiency -- 6.4 Technology Implications and Trends -- 6.4.1 System Partitioning-Discrete Devices versus Integrated Circuits and Other Considerations -- 6.5 Current Technologies and Capabilities -- 6.5.1 Discrete Power Technologies and Trends -- 6.5.1.1 IGBT -- 6.5.1.2 Power MOSFET -- 6.5.2 Integrated Circuit Power Technology and Trends -- 6.5.2.1 Power Processes -- 6.5.2.2 Digital Logic Technology -- 6.6 Specific Application Example -- 6.7 Emerging Technologies -- 6.8 Conclusion -- References -- 7 ULTRALOW POWER MANAGEMENT CIRCUIT FOR OPTIMAL ENERGY HARVESTING IN WIRELESS BODY AREA NETWORK -- 7.1 Introduction -- 7.2 Wireless Body Area Network -- 7.2.1 Wireless Sensor Node in WBAN -- 7.2.2 Embedded System -- 7.2.3 Design Challenges of WBAN -- 7.2.4 Potential Applications of WBAN -- 7.2.5 Other Group's Work -- 7.2.6 An Ultralow Power ECG Acquisition and Monitoring ASIC System for WBAN Application.

7.3 Optimal Energy Harvesting System -- 7.3.1 Energy Harvesting Basics -- 7.3.2 Solar Energy Harvesting Technique -- 7.3.3 Maximum Power Point Tracking (MPPT) Based Power Management Circuit -- 7.4 Ultralow Power Management Integrated Circuit for Solar Energy Harvesting System -- 7.5 Conclusions -- References -- PART II: ANALOG AND RF DESIGN -- 8 ANALOG CIRCUIT DESIGN FOR SOI -- 8.1 SOI Devices -- 8.2 Partially Depleted SOI -- 8.3 FDSOI and FinFET -- 8.4 Device Considerations (FDSOI AND PDSOI) -- 8.4.1 Self-Heating and Dissipation within a Device -- 8.4.1.1 DC Heating from Elsewhere on the Same Chip -- 8.4.1.2 Transient or AC Thermal Coupling -- 8.4.2 Design Choice: SOI or Bulk? -- 8.4.3 Benefits of SOI for Analog Design -- 8.4.4 Drawbacks of Analog Design on SOI -- 8.5 Analog Circuit Building Blocks -- 8.5.1 Current Mirrors -- 8.5.2 Global Variation -- 8.5.3 Cascoded Current Mirrors -- 8.5.4 Wilson Current Mirror -- 8.5.5 Circuit Effects of High Temperature Leakage -- 8.5.6 Circuit Thermal Coupling Effects -- 8.5.6.1 DC Thermal Coupling in Current Mirrors -- 8.5.6.2 Transient Thermal Coupling in Current Mirrors -- 8.6 Operational Amplifiers -- 8.6.1 Common Mode Gain -- 8.6.2 Reducing the Common Mode Effect -- 8.7 Operational Transconductance Amplifier -- 8.7.1 Analog Circuits -- 8.7.1.1 Bandgap -- 8.7.1.2 Charge Pump Circuitry -- 8.7.1.3 Output Stages/Buffers -- 8.7.2 High Voltage and Power Applications -- 8.7.3 Sample and Hold Circuitry -- 8.7.4 Circuits for RF/Wireless Applications -- 8.8 Radio Frequency Low-Noise Amplifier -- 8.9 Mixers and Analog Multipliers -- 8.9.1 Delay Locked Loop and Phase Locked Loop -- 8.9.2 Oscillators -- 8.9.3 Voltage Regulation -- 8.9.3.1 Series Regulator -- 8.9.3.2 LDO Regulator -- 8.10 Analog to Digital and Digital to Analog Converters -- 8.10.1 Sigma Delta Modulation -- 8.11 Summary -- References.

9 FREQUENCY GENERATION AND CONTROL WITH SELF-REFERENCED CMOS OSCILLATORS -- 9.1 Introduction -- 9.1.1 Critical Performance Metrics -- 9.1.2 Application Requirements -- 9.2 Self-Referenced CMOS Oscillators -- 9.2.1 Noise -- 9.2.2 Native Frequency Drift Mechanisms -- 9.2.3 Frequency-Trimming and Temperature-Compensation -- 9.2.4 Spread-Spectrum Clock Generation -- 9.2.5 Design Considerations -- 9.2.6 Production Test and Built-In Test Circuitry -- 9.2.7 State-of-the-Art Performance of the Native Silicon -- 9.3 Packaging -- 9.3.1 Package-Induced Frequency Drift -- 9.3.2 A Wafer-Scale Post-Processes to Contain Package-Induced Frequency Drift -- 9.3.3 Quality and Reliability -- 9.3.4 Embodiments -- 9.4 Conclusion -- References -- 10 SYNTHESIS OF STATIC AND DYNAMIC TRANSLINEAR CIRCUITS -- 10.1 Translinear Circuits: What Is In a Name? -- 10.2 The Scope of Translinear Circuits -- 10.3 Static and Dynamic Translinear Circuit Synthesis -- 10.4 Static Translinear Circuit Synthesis Examples -- 10.4.1 Square-Rooting Circuit -- 10.4.2 Two-Quadrant Squaring Circuit -- 10.4.2.1 Class-A Two-Quadrant Squaring Circuit -- 10.4.2.2 Class-AB Two-Quadrant Squaring Circuit -- 10.4.2.3 Sinh/Cosh Two-Quadrant Squaring Circuit -- 10.4.2.4 Discussion -- 10.4.3 Four-Quadrant Pythagorator -- 10.5 Dynamic Translinear Circuit Synthesis Examples -- 10.5.1 First-Order Low-Pass Filter -- 10.5.1.1 Inverting Output Structure -- 10.5.1.2 Noninverting Output Structures -- 10.5.1.3 Discussion -- 10.5.2 Second-Order Low-Pass Filter -- 10.5.3 RMS-to-DC Converter -- References -- 11 MICROWATT POWER CMOS ANALOG CIRCUIT DESIGNS: ULTRALOW POWER LSIs FOR POWER-AWARE APPLICATIONS -- 11.1 Introduction -- 11.2 Subthreshold Characteristics in a MOSFET -- 11.2.1 The Basics -- 11.2.1.1 Current in the Subthreshold Region -- 11.2.1.2 Current in the Strong Inversion Region -- 11.2.2 Temperature Dependence.

11.2.2.1 T.C. of the Current in the Subthreshold Region.